 | 1997 |
|---|
| 7 |       | Carsten Reuter,
Markus Schwiegershausen,
Peter Pirsch:
Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms.
ASAP 1997: 294-303 |
| 6 |  | Tien-Toan Do,
Holger Kropp,
Markus Schwiegershausen,
Peter Pirsch:
Implementation of pipelined multipliers on Xilinx FPGAs.
FPL 1997: 51-60 |
| 1995 |
|---|
| 5 | | Markus Schwiegershausen,
Peter Pirsch:
A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes.
EURO-DAC 1995: 8-13 |
| 4 | | Markus Schwiegershausen,
Peter Pirsch:
A system level design methodology for the optimization of heterogeneous multiprocessors.
ISSS 1995: 162-169 |
| 3 | | Mirjam Schönfeld,
Jens Franzen,
Markus Schwiegershausen,
Peter Pirsch,
Uwe Vehlies,
Andreas Münzner:
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques.
VLSI Signal Processing 11(1-2): 51-74 (1995) |
| 1991 |
|---|
| 2 | | Mirjam Schönfeld,
Markus Schwiegershausen,
Peter Pirsch:
Synthesis of intermediate memories for the data supply to processor arrays.
Algorithms and Parallel VLSI Architectures 1991: 365-370 |
| 1 | | Mirjam Schönfeld,
Markus Schwiegershausen,
Peter Pirsch:
Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays.
VLSI 1991: 297-306 |
