 | 2009 |
| 18 |  | Zahra Sasanian,
Mehdi Saeedi,
Mehdi Sedighi,
Morteza Saheb Zamani:
A cycle-based synthesis algorithm for reversible logic.
ASP-DAC 2009: 745-750 |
| 2008 |
| 17 |  | Mehdi Saeedi,
Morteza Saheb Zamani,
Mehdi Sedighi:
Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms.
ASP-DAC 2008: 83-88 |
| 16 |  | Mehdi Saeedi,
Naser MohammadZadeh,
Mehdi Sedighi,
Morteza Saheb Zamani:
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics.
DSD 2008: 490-493 |
| 15 |  | Ehsan K. Ardestani,
Morteza Saheb Zamani,
Mehdi Sedighi:
A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits.
DSD 2008: 803-806 |
| 14 |  | Mahdi Aminian,
Mehdi Saeedi,
Morteza Saheb Zamani,
Mehdi Sedighi:
FPGA-Based Circuit Model Emulation of Quantum Algorithms.
ISVLSI 2008: 399-404 |
| 2007 |
| 13 |  | Mehdi Saeedi,
Morteza Saheb Zamani,
Mehdi Sedighi:
Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis.
DSD 2007: 339-346 |
| 12 |  | Mehdi Saeedi,
Mehdi Sedighi,
Morteza Saheb Zamani:
A novel synthesis algorithm for reversible circuits.
ICCAD 2007: 65-68 |
| 11 |  | Mehdi Saeedi,
Morteza Saheb Zamani,
Mehdi Sedighi:
On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement.
ISVLSI 2007: 428-436 |
| 2006 |
| 10 |  | Farhad Mehdipour,
Hamid Noori,
Morteza Saheb Zamani,
Kazuaki Murakami,
Mehdi Sedighi,
Koji Inoue:
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit.
Asia-Pacific Computer Systems Architecture Conference 2006: 219-230 |
| 9 |  | Farhad Mehdipour,
Morteza Saheb Zamani,
Mehdi Sedighi,
Kazuaki Murakami,
Hamid Noori:
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs.
ERSA 2006: 227-230 |
| 8 |  | Farhad Mehdipour,
Hamid Noori,
Morteza Saheb Zamani,
Kazuaki Murakami,
Koji Inoue,
Mehdi Sedighi:
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit.
EUC 2006: 722-731 |
| 7 |  | Farhad Mehdipour,
Morteza Saheb Zamani,
H. R. Ahmadifar,
Mehdi Sedighi,
Kazuaki Murakami:
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework.
IPDPS 2006 |
| 6 |  | Farhad Mehdipour,
Morteza Saheb Zamani,
Mehdi Sedighi:
An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems.
Microprocessors and Microsystems 30(1): 52-62 (2006) |
| 2005 |
| 5 |  | Kamran Saleh,
Mehrdad Najibi,
Mohsen Naderi,
Hossein Pedram,
Mehdi Sedighi:
A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach.
ACM Great Lakes Symposium on VLSI 2005: 296-301 |
| 4 |  | Hamid Safizadeh,
Hamid Noori,
Mehdi Sedighi,
Ali Jahanian,
Neda Zolfaghari:
Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms.
DSD 2005: 227-230 |
| 3 |  | Farhad Mehdipour,
Morteza Saheb Zamani,
Mehdi Sedighi:
Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems.
DSD 2005: 372-378 |
| 2 |  | Mehrdad Najibi,
Kamran Saleh,
Mohsen Naderi,
Hossein Pedram,
Mehdi Sedighi:
Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only).
FPGA 2005: 269 |
| 1 |  | Mehrdad Najibi,
Kamran Saleh,
Mohsen Naderi,
Hossein Pedram,
Mehdi Sedighi:
Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs.
IEEE International Workshop on Rapid System Prototyping 2005: 63-69 |