G. Seetharaman

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2009

2 V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani: Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. VLSI Design 2009: 473-478

1 G. Seetharaman, B. Venkataramani: Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. TRETS 2(2): (2009)

	2009
2		V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani: Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. VLSI Design 2009: 473-478
1		G. Seetharaman, B. Venkataramani: Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. TRETS 2(2): (2009)

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