| 2009 | ||
|---|---|---|
| 54 | Ramana C. Jandhyala, Mukkai S. Krishnamoorthy, George Nagy, Raghav K. Padmanabhan, Sharad C. Seth, William Silversmith: From Tessellations to Table Interpretation. Calculemus/MKM 2009: 422-437 | |
| 53 | George Nagy, Sharad C. Seth, Mahesh Viswanathan: Comment: Projection Methods Require Black Border Removal. IEEE Trans. Pattern Anal. Mach. Intell. 31(4): 762 (2009) | |
| 2008 | ||
| 52 | Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram: Efficient Selection of Observation Points for Functional Tests. ISQED 2008: 236-241 | |
| 51 | Sharad C. Seth, Ashok Samal: Conflation of Features. Encyclopedia of GIS 2008: 129-133 | |
| 50 | Ashok Samal, Sharad C. Seth: Feature Extraction, Abstract. Encyclopedia of GIS 2008: 314-320 | |
| 49 | Indranil Saha, Bhargab B. Bhattacharya, Sheng Zhang, Sharad C. Seth: Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid. Fundam. Inform. 89(2-3): 331-344 (2008) | |
| 2007 | ||
| 48 | Jian Kang, Sharad C. Seth, Vijay Gangaram: Efficient RTL Coverage Metric for Functional Test Selection. VTS 2007: 318-324 | |
| 2006 | ||
| 47 | Ashutosh Joshi, George Nagy, Daniel P. Lopresti, Sharad C. Seth: A Maximum-Likelihood Approach to Symbolic Indirect Correlation. ICPR (3) 2006: 99-103 | |
| 2005 | ||
| 46 | Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya: Efficient Test Compaction for Pseudo-Random Testing. Asian Test Symposium 2005: 337-342 | |
| 45 | Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya: On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design. VLSI Design 2005: 491-496 | |
| 2004 | ||
| 44 | George Nagy, Ashutosh Joshi, Mukkai S. Krishnamoorthy, Yu Lin, Daniel P. Lopresti, Shashank K. Mehta, Sharad C. Seth: A nonparametric classifier for unsegmented text. DRR 2004: 102-108 | |
| 43 | Ashok Samal, Sharad C. Seth, Kevin Cueto: A feature-based approach to conflation of geospatial sources. International Journal of Geographical Information Science 18(5): 459-489 (2004) | |
| 2003 | ||
| 42 | Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang: Double-Tree Scan: A Novel Low-Power Scan-Path Architecture. ITC 2003: 470-479 | |
| 41 | Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang: Low-Energy BIST Design for Scan-based Logic Circuits. VLSI Design 2003: 546-551 | |
| 40 | Hailong Cui, Sharad C. Seth, Shashank K. Mehta: Modeling Fault Coverage of Random Test Patterns. J. Electronic Testing 19(3): 271-284 (2003) | |
| 2002 | ||
| 39 | Hailong Cui, Sharad C. Seth, Shashank K. Mehta: A Novel Method to Improve the Test Efficiency of VLSI Tests. VLSI Design 2002: 499-504 | |
| 2001 | ||
| 38 | Don Sylwester, Sharad C. Seth: Adaptive Segmentation of Document Images. ICDAR 2001: 827-831 | |
| 37 | Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr: Design Verification and Functional Testing of FiniteState Machines. VLSI Design 2001: 189-195 | |
| 2000 | ||
| 36 | Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr: Exploiting don't cares to enhance functional tests. ITC 2000: 538-546 | |
| 35 | Luyang Li, George Nagy, Ashok Samal, Sharad C. Seth, Yihong Xu: Integrated text and line-art extraction from a topographic map. IJDAR 2(4): 177-185 (2000) | |
| 1999 | ||
| 34 | Luyang Li, George Nagy, Ashok Samal, Sharad C. Seth, Yihong Xu: Cooperative Text and Line-Art Extraction from a Topographic Map. ICDAR 1999: 467-470 | |
| 33 | Shashank K. Mehta, Sharad C. Seth: Empirical Computation of Reject Ratio in VLSI Testing. VLSI Design 1999: 506-511 | |
| 32 | Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth: A synthesis for testability scheme for finite state machines using clock control. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1780-1792 (1999) | |
| 1998 | ||
| 31 | Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth: Synthesis of Sequential Circuits with Clock Control to Improve Testability. Asian Test Symposium 1998: 472- | |
| 30 | Vishwani D. Agrawal, Sharad C. Seth: Mutually Disjoint Signals and Probability Calculation in Digital Circuits. Great Lakes Symposium on VLSI 1998: 307-312 | |
| 1997 | ||
| 29 | George Nagy, Ashok Samal, Sharad C. Seth, T. Fisher, E. Guthmann, K. Kalafala, Luyang Li, Prateek Sarkar, S. Sivasubramaniam, Yihong Xu: A Prototype for Adaptive Association of Street Names with Streets on Maps. GREC 1997: 302-313 | |
| 28 | Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth: Synthesis for Testability by Two-Clock Control. VLSI Design 1997: 279-283 | |
| 1996 | ||
| 27 | Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal: Improving Circuit Testability by Clock Control. Great Lakes Symposium on VLSI 1996: 288-293 | |
| 1995 | ||
| 26 | Stephen D. Scott, Ashok Samal, Sharad C. Seth: HGA: A Hardware-Based Genetic Algorithm. FPGA 1995: 53-59 | |
| 25 | Don Sylwester, Sharad C. Seth: A trainable, single-pass algorithm for column segmentation. ICDAR 1995: 615-618 | |
| 24 | Yuhong Yu, Ashok Samal, Sharad C. Seth: A system for recognizing a large class of engineering drawings. ICDAR 1995: 791-794 | |
| 23 | S. Venkatraman, Sharad C. Seth, Prathima Agrawal: Parallel test generation with low communication overhead. VLSI Design 1995: 116-120 | |
| 22 | N. Ranganathan, Sharad C. Seth: Conference Reports. IEEE Design & Test of Computers 12(2): 5, 81 (1995) | |
| 21 | Kent L. Einspahr, Sharad C. Seth: A switch-level test generation system for synchronous and asynchronous circuits. J. Electronic Testing 6(1): 59-73 (1995) | |
| 1994 | ||
| 20 | Sharad C. Seth, Lee Gowen, Matt Payne, Don Sylwester: Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine. VLSI Design 1994: 29-32 | |
| 19 | Yuhong Yu, Ashok Samal, Sharad C. Seth: Isolating symbols from connection lines in a class of engineering drawings. Pattern Recognition 27(3): 391-404 (1994) | |
| 1993 | ||
| 18 | Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth: Generating Tests for Delay Faults in Nonscan Circuits. IEEE Design & Test of Computers 10(1): 20-28 (1993) | |
| 17 | Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth, Mahesh Viswanathan: Syntactic Segmentation and Labeling of Digitized Pages from Technical Journals. IEEE Trans. Pattern Anal. Mach. Intell. 15(7): 737-747 (1993) | |
| 16 | D. Das, Sharad C. Seth, Vishwani D. Agrawal: Accurate computation of field reject ratio based on fault latency. IEEE Trans. VLSI Syst. 1(4): 537-545 (1993) | |
| 1992 | ||
| 15 | George Nagy, Sharad C. Seth, Mahesh Viswanathan: A Prototype Document Image Analysis System for Technical Journals. IEEE Computer 25(7): 10-22 (1992) | |
| 1991 | ||
| 14 | Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal: Estimating the Quality of Manufactured Digital Sequential Circuits. ITC 1991: 210-217 | |
| 1990 | ||
| 13 | Paul Kenyon, Prathima Agrawal, Sharad C. Seth: High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator. MICRO 1990: 97-106 | |
| 12 | Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat: A Statistical Theory of Digital Circuit Testability. IEEE Trans. Computers 39(4): 582-586 (1990) | |
| 1989 | ||
| 11 | Raghu V. Hudli, Sharad C. Seth: Testability Analysis of Synchronous Sequential Circuits Based on Structural Data. ITC 1989: 364-372 | |
| 10 | Lester Lipsky, Sharad C. Seth: Signal Probabilities in AND-OR Trees. IEEE Trans. Computers 38(11): 1558-1563 (1989) | |
| 9 | Bhargab B. Bhattacharya, Sharad C. Seth: Design of Parity Testable Combinational Circuits. IEEE Trans. Computers 38(11): 1580-1584 (1989) | |
| 1985 | ||
| 8 | Sharad C. Seth: Predicting Fault Coverage from Probabilistic Testability. ITC 1985: 803-807 | |
| 1984 | ||
| 7 | Ten-Chuan Hsiao, Sharad C. Seth: An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing. IEEE Trans. Computers 33(10): 934-937 (1984) | |
| 6 | Sharad C. Seth, Vishwani D. Agrawal: Characterizing the LSI Yield Equation from Wafer Test Data. IEEE Trans. on CAD of Integrated Circuits and Systems 3(2): 123-126 (1984) | |
| 1983 | ||
| 5 | Sharad C. Seth, Lester Lipsky: A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems. IEEE Trans. Computers 32(8): 754-760 (1983) | |
| 1981 | ||
| 4 | Sharad C. Seth, K. Narayanaswamy: A Graph Model for Pattern-Sensitive Faults in Random Access Memories. IEEE Trans. Computers 30(12): 973-977 (1981) | |
| 1978 | ||
| 3 | Kolar L. Kodandapani, Sharad C. Seth: On Combinational Networks with Restricted Fan-Out. IEEE Trans. Computers 27(4): 309-318 (1978) | |
| 1977 | ||
| 2 | Sharad C. Seth, Kolar L. Kodandapani: Diagnosis of Faults in Linear Tree Networks. IEEE Trans. Computers 26(1): 29-33 (1977) | |
| 1 | James M. Steckelberg, Sharad C. Seth: On a Relation Between Algebraic Programs and Turing Machines. Inf. Process. Lett. 6(6): 180-183 (1977) | |