Kenshu Seto

	2009
9		Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. IEICE Transactions 92-A(6): 1464-1475 (2009)
	2008
8		Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki: SAT-based resource binding for reducing critical path delays. FPL 2008: 507-510
7		Kenshu Seto, Masahiro Fujita: Custom Instruction Generation with High-Level Synthesis. SASP 2008: 14-19
	2007
6		Shigeru Watanabe, Kenshu Seto, Y. Ishikawa, Satoshi Komatsu, Masahiro Fujita: Protocol Transducer Synthesis using Divide and Conquer approach. ASP-DAC 2007: 280-285
5		Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. IESS 2007: 121-134
	2005
4		Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. FPT 2005: 137-144
	2003
3		Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima: Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. HICSS 2003: 279
2		Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita: Engineering Changes in Field Modifiable Architectures. MEMOCODE 2003: 87-94
	2002
1		Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS 2002: 103-108

Coauthor Index

1	Masahiro Fujita	[1] [2] [3] [4] [5] [6] [7] [9]
2	Shanghua Gao	[4] [5] [9]
3	Y. Ishikawa	[6]
4	Yoshihisa Kojima	[1] [2] [3]
5	Satoshi Komatsu	[1] [2] [3] [4] [5] [6] [9]
6	Takuya Maruizumi	[8]
7	Yuta Nonaka	[8]
8	Hiroshi Saito	[1] [2] [3]
9	Thanyapat Sakunkonchak	[3]
10	Yasuhiro Shiraki	[8]
11	Shigeru Watanabe	[6]
12	Hiroaki Yoshida	[9]

Colors in the list of coauthors