Jatan P. Shah

	2008
3		Rama Sangireddy, Jatan P. Shah: Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC. IEEE Trans. Parallel Distrib. Syst. 19(4): 529-544 (2008)
	2007
2		Jatan P. Shah, Rama Sangireddy: Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. ISCAS 2007: 4012-4015
	2006
1		Prabhu Rajamani, Jatan P. Shah, Vadhiraj Sankaranarayanan, Rama Sangireddy: High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization. IPCCC 2006

Coauthor Index

1	Prabhu Rajamani	[1]
2	Rama Sangireddy	[1] [2] [3]
3	Vadhiraj Sankaranarayanan	[1]