 | 2007 |
|---|
| 12 |       | Salem Abdennadher,
Saghir A. Shaikh:
Practices in Mixed-Signal and RF IC Testing.
IEEE Design & Test of Computers 24(4): 332-339 (2007) |
| 2005 |
|---|
| 11 | | Salem Abdennadher,
Saghir A. Shaikh:
Practices in Testing of Mixed-Signal and RF SoCs.
Asian Test Symposium 2005: 467 |
| 10 | | Salem Abdennadher,
Saghir A. Shaikh:
Challenges in High Speed Interface Testing.
Asian Test Symposium 2005: 468 |
| 2004 |
|---|
| 9 | | Saghir A. Shaikh:
IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver.
ITC 2004: 543-550 |
| 2001 |
|---|
| 8 |  | John T. Chen,
Jitendra Khare,
Ken Walker,
Saghir A. Shaikh,
Janusz Rajski,
Wojciech Maly:
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring.
ITC 2001: 258-267 |
| 2000 |
|---|
| 7 | | Saghir A. Shaikh,
Jitendra Khare,
Hans T. Heineken:
Manufacturability and Testability Oriented Synthesis.
VLSI Design 2000: 185-191 |
| 6 | | Charles H. Ouyang,
Hans T. Heineken,
Jitendra Khare,
Saghir A. Shaikh,
M. d'Abreu:
Maximizing Wafer Productivity Through Layout Optimization.
VLSI Design 2000: 192-197 |
| 5 | | A. Bommireddy,
Jitendra Khare,
Saghir A. Shaikh,
S.-T. Su:
Test and Debug of Networking SoCs: A Case Study.
VTS 2000: 121-126 |
| 1997 |
|---|
| 4 | | Youngmin Hur,
Saghir A. Shaikh,
Silvian Goldenberg,
D. Kacprzak,
Stephen A. Szygenda:
Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System.
Annual Simulation Symposium 1997: 168-176 |
| 3 | | Saghir A. Shaikh,
Stephen A. Szygenda:
Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation.
Annual Simulation Symposium 1997: 64- |
| 1996 |
|---|
| 2 | | Saghir A. Shaikh,
Silvian Goldenberg,
Stephen A. Szygenda:
CON2FERS: A Concurrent Concurrent Fault and Design Error Simulator.
PDPTA 1996: 109-112 |
| 1995 |
|---|
| 1 | | Brian Grayson,
Saghir A. Shaikh,
Stephen A. Szygenda:
Statistics on concurrent fault and design error simulation.
ICCD 1995: 622-627 |
