Naresh R. Shanbhag

	2008
71		Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones: Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip. ACM Great Lakes Symposium on VLSI 2008: 351-354
70		Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones: Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. ISCAS 2008: 380-383
69		Rami A. Abdallah, Naresh R. Shanbhag: Error-resilient low-power Viterbi decoders. ISLPED 2008: 111-116
68		Rami A. Abdallah, Naresh R. Shanbhag: Error-resilient low-power Viterbi decoders via state clustering. SiPS 2008: 221-226
67		Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet Roychowdhury, Douglas L. Jones, Jan M. Rabaey: The Search for Alternative Computational Paradigms. IEEE Design & Test of Computers 25(4): 334-343 (2008)
66		Girish Varatkar, Naresh R. Shanbhag: Error-Resilient Motion Estimation Architecture. IEEE Trans. VLSI Syst. 16(10): 1399-1412 (2008)
65		Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag: Joint Equalization and Coding for On-Chip Bus Communication. IEEE Trans. VLSI Syst. 16(3): 314-318 (2008)
	2007
64		Girish Varatkar, Naresh R. Shanbhag: Variation-Tolerant Motion Estimation Architecture. SiPS 2007: 126-131
63		Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 977-982 (2007)
	2006
62		Girish Varatkar, Naresh R. Shanbhag: Energy-efficient motion estimation using error-tolerance. ISLPED 2006: 113-118
61		Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel: Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. VLSI Syst. 14(12): 1368-1378 (2006)
60		Byonghyo Shim, Naresh R. Shanbhag: Energy-efficient soft error-tolerant digital signal processing. IEEE Trans. VLSI Syst. 14(4): 336-348 (2006)
59		Ming Zhang, Naresh R. Shanbhag: Soft-Error-Rate-Analysis (SERA) Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2140-2155 (2006)
	2005
58		Ming Zhang, Naresh R. Shanbhag: An energy-efficient circuit technique for single event transient noise-tolerance. ISCAS (1) 2005: 636-639
57		Srinivasa R. Sridhara, Naresh R. Shanbhag: A low-power bus design using joint repeater insertion and coding. ISLPED 2005: 99-102
56		Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan: Joint Equalization and Coding for On-Chip Bus Communication. ISQED 2005: 642-647
55		Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. VLSI Design 2005: 417-422
54		Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for system-on-chip networks: a unified framework. IEEE Trans. VLSI Syst. 13(6): 655-667 (2005)
53		Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: Area-efficient high-throughput MAP decoder architectures. IEEE Trans. VLSI Syst. 13(8): 921-933 (2005)
52		Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag: Linear turbo equalization analysis via BER transfer and EXIT charts. IEEE Transactions on Signal Processing 53(8-1): 2883-2897 (2005)
51		Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: Energy Efficient VLSI Architecture for Linear Turbo Equalizer. VLSI Signal Processing 39(1-2): 49-62 (2005)
50		Naresh R. Shanbhag, Keshab K. Parhi: Guest Editorial. VLSI Signal Processing 39(1-2): 5-6 (2005)
49		Mohammad M. Mansour, Naresh R. Shanbhag: A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes. VLSI Signal Processing 40(3): 371-382 (2005)
	2004
48		Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for system-on-chip networks: a unified framework. DAC 2004: 103-106
47		Naresh R. Shanbhag: A communication-theoretic design paradigm for reliable SOCs. DAC 2004: 76
46		Ming Zhang, Naresh R. Shanbhag: A soft error rate analysis (SERA) methodology. ICCAD 2004: 111-118
45		Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag: Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. ICCD 2004: 12-17
44		Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: Switching methods for linear turbo equalization. ISCAS (3) 2004: 601-604
43		Naresh R. Shanbhag: Reliable and Efficient System-on-Chip Design. IEEE Computer 37(3): 42-50 (2004)
42		Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag: Reliable low-power digital signal processing via reduced precision redundancy. IEEE Trans. VLSI Syst. 12(5): 497-510 (2004)
	2003
41		Ganesh Balamurugan, Naresh R. Shanbhag: Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. ICCD 2003: 254-260
40		Hyeon-Min Bae, Naresh R. Shanbhag: High bandwidth transimpedance amplifier design using active transmission lines. ISCAS (1) 2003: 253-256
39		Mohammad M. Mansour, Naresh R. Shanbhag: Architecture-aware low-density parity-check codes. ISCAS (2) 2003: 57-60
38		Byonghyo Shim, Naresh R. Shanbhag: Performance analysis of algorithmic noise-tolerance techniques. ISCAS (4) 2003: 113-116
37		Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: A low-power VLSI architecture for turbo decoding. ISLPED 2003: 366-371
36		Lei Wang, Naresh R. Shanbhag: Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise. IEEE Trans. VLSI Syst. 11(2): 254-269 (2003)
35		Lei Wang, Naresh R. Shanbhag: Low-power MIMO signal processing. IEEE Trans. VLSI Syst. 11(3): 434-445 (2003)
34		Mohammad M. Mansour, Naresh R. Shanbhag: VLSI architectures for SISO-APP decoders. IEEE Trans. VLSI Syst. 11(4): 627-650 (2003)
33		Mohammad M. Mansour, Naresh R. Shanbhag: High-throughput LDPC decoders. IEEE Trans. VLSI Syst. 11(6): 976-996 (2003)
	2002
32		Naresh R. Shanbhag: Reliable and energy-efficient digital signal processing. DAC 2002: 830-835
31		Mohammad M. Mansour, Naresh R. Shanbhag: Simplified current and delay models for deep submicron CMOS digital circuits. ISCAS (5) 2002: 109-112
30		Mohammad M. Mansour, Naresh R. Shanbhag: Low-power VLSI decoder architectures for LDPC codes. ISLPED 2002: 284-289
	2001
29		Lei Wang, Naresh R. Shanbhag: Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers. ISLPED 2001: 334-339
28		Dilip V. Sarwate, Naresh R. Shanbhag: High-speed architectures for Reed-Solomon decoders. IEEE Trans. VLSI Syst. 9(5): 641-655 (2001)
27		Rajamohana Hegde, Naresh R. Shanbhag: Soft digital signal processing. IEEE Trans. VLSI Syst. 9(6): 813-823 (2001)
26		Swaroop Appadwedula, Manish Goel, Naresh R. Shanbhag, Douglas L. Jones, Kannan Ramchandran: Total System Energy Minimization for Wireless Image Transmission. VLSI Signal Processing 27(1-2): 99-117 (2001)
25		Wayne Burleson, Naresh R. Shanbhag: Guest Editorial: Reconfigurable Signal Processing Systems. VLSI Signal Processing 28(1-2): 5-6 (2001)
	2000
24		Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang: Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321
23		Naresh R. Shanbhag, K. Soumyanath, Samuel Martin: Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). ISLPED 2000: 295-302
22		Rajamohana Hegde, Naresh R. Shanbhag: Toward achieving energy efficiency in presence of deep submicron noise. IEEE Trans. VLSI Syst. 8(4): 379-391 (2000)
	1999
21		Lei Wang, Naresh R. Shanbhag: Noise-tolerant dynamic circuit design. ISCAS (1) 1999: 549-552
20		Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Low-power distributed arithmetic architectures using nonuniform memory partitioning. ISCAS (3) 1999: 470-473
19		Rajamohana Hegde, Naresh R. Shanbhag: Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI. ISCAS (6) 1999: 334-337
18		Ganesh Balamurugan, Naresh R. Shanbhag: Energy-efficient dynamic circuit design in the presence of crosstalk noise. ISLPED 1999: 24-29
17		Rajamohana Hegde, Naresh R. Shanbhag: Energy-efficient signal processing via algorithmic noise-tolerance. ISLPED 1999: 30-35
16		Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag: Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. VLSI Design 1999: 358-
15		Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: A coding framework for low-power address and data busses. IEEE Trans. VLSI Syst. 7(2): 212-221 (1999)
14		Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Information-theoretic bounds on average signal transition activity [VLSI systems]. IEEE Trans. VLSI Syst. 7(3): 359-368 (1999)
13		Manish Goel, Naresh R. Shanbhag: Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing. IEEE Trans. VLSI Syst. 7(4): 463-476 (1999)
	1998
12		Rajamohana Hegde, Naresh R. Shanbhag: Energy-efficiency in presence of deep submicron noise. ICCAD 1998: 228-234
11		Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Decorrelating (DECOR) transformations for low-power adaptive filters. ISLPED 1998: 250-255
10		Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. VLSI Design 1998: 18-23
	1997
9		Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Analytical Estimation of Transition Activity From Word-Level Signal Statistics. DAC 1997: 582-587
8		Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Achievable bounds on signal transition activity. ICCAD 1997: 126-129
7		Manish Goel, Naresh R. Shanbhag: Dynamic algorithm transformation (DAT) for low-power adaptive signal processing. ISLPED 1997: 161-166
6		Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Analytical estimation of signal transition activity from word-level statistics. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 718-733 (1997)
	1996
5		Manish Goel, Naresh R. Shanbhag: Low-power adaptive filter architectures via strength reduction. ISLPED 1996: 217-220
4		Naresh R. Shanbhag: Lower bounds on power dissipation for DSP algorithms. ISLPED 1996: 43-48
	1995
3		Naresh R. Shanbhag, Gi-Hong Im: Pipelined Adaptive IIR Filter Architecture. ISCAS 1995: 558-561
	1993
2		Naresh R. Shanbhag, Keshab K. Parhi: A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications. ISCAS 1993: 1956-1958
1		Naresh R. Shanbhag, Keshab K. Parhi: Roundoff error analysis of the pipelined ADPCM coder. ISCAS 1993: 886-889

Coauthor Index

1	Rami A. Abdallah	[68] [69]
2	Arshad Ahmed	[45]
3	Swaroop Appadwedula	[26]
4	Hyeon-Min Bae	[40]
5	Kwang-Hyun Baek	[24]
6	Ganesh Balamurugan	[18] [41] [56] [65]
7	Sudhakar Bobba	[16]
8	Wayne P. Burleson (Wayne Burleson)	[25]
9	Manish Goel	[5] [7] [13] [26]
10	Ibrahim N. Hajj	[6] [8] [9] [10] [11] [14] [15] [16] [20]
11	Rajamohana Hegde	[12] [17] [19] [22] [27]
12	Gi-Hong Im	[3]
13	Douglas L. Jones	[26] [67] [70] [71]
14	Sung-Mo Kang	[24]
15	Kee Sup Kim	[61]
16	Ki-Wook Kim	[24]
17	Seok-Jun Lee	[37] [44] [51] [52] [53]
18	C. L. Liu (Chung Laung (Dave) Liu)	[24]
19	T. M. Mak	[61]
20	Mohammad M. Mansour	[30] [31] [33] [34] [39] [49]
21	Radu Marculescu	[67]
22	Samuel Martin	[23]
23	Subhasish Mitra	[61] [67]
24	Sriram Narayanan	[70] [71]
25	Michael Orshansky	[67]
26	Keshab K. Parhi	[1] [2] [50]
27	S. J. Patel	[61]
28	Jan M. Rabaey	[67]
29	Kannan Ramchandran	[26]
30	Sumant Ramprasad	[6] [8] [9] [10] [11] [14] [15] [20]
31	Jaijeet Roychowdhury	[67]
32	Dilip V. Sarwate	[28]
33	Norbert Seifert	[61]
34	Quan Shi	[61]
35	Byonghyo Shim	[38] [42] [60]
36	Andrew C. Singer	[37] [44] [51] [52] [53]
37	K. Soumyanath	[23]
38	Srinivasa R. Sridhara	[42] [45] [48] [54] [55] [56] [57] [63] [65]
39	Girish Varatkar	[62] [64] [66] [70] [71]
40	Gustavo de Veciana	[67]
41	Lei Wang	[21] [29] [35] [36]
42	N. J. Wang	[61]
43	Ming Zhang	[46] [58] [59] [61]

Colors in the list of coauthors