K. R. Shesha Shayee

	2004
3		Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee: Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. IEEE Trans. Computers 53(11): 1420-1435 (2004)
	2003
2		K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz: Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations. FCCM 2003: 296
1		K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz: Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. FPL 2003: 313-323

Coauthor Index

1	Pedro C. Diniz	[1] [2] [3]
2	Joonseok Park	[1] [2] [3]