Narendra V. Shenoy

	2008
35		Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED 2008: 379-384
34		Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED 2008: 450-455
	2007
33		Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou: Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880
32		Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1522-1533 (2007)
	2006
31		Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Random Variables. ISQED 2006: 306-311
30		Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. VLSI Syst. 14(10): 1140-1146 (2006)
	2005
29		Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical gate sizing for timing yield optimization. ICCAD 2005: 1037-1041
	2004
28		Narendra V. Shenoy, Jamil Kawa, Raul Camposano: Design automation for mask programmable fabrics. DAC 2004: 192-197
27		Shabbir H. Batterywala, Narendra V. Shenoy: Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. VLSI Design 2004: 989-994
	2003
26		Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei: Emerging markets: design goes global. DAC 2003: 195
25		Shabbir H. Batterywala, Narendra V. Shenoy: A Method to Estimate Slew and Delay in Coupled Digital Circuits. VLSI Design 2003: 411-416
	2002
24		Narendra V. Shenoy, William Nicholls: An efficient routing database. DAC 2002: 590-595
23		Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou: Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD 2002: 59-66
22		Stan Y. Liao, Narendra V. Shenoy, William Nicholls: An Efficient External-Memory Implementation of Region Query with Application to Area Routing. ICCD 2002: 36-41
21		Hai Zhou, Narendra V. Shenoy, William Nicholls: Efficient minimum spanning tree construction without Delaunay triangulation. Inf. Process. Lett. 81(5): 271-276 (2002)
	2001
20		Hai Zhou, Narendra V. Shenoy, William Nicholls: Efficient minimum spanning tree construction without Delaunay triangulation. ASP-DAC 2001: 192-197
19		Hai Zhou, Narendra V. Shenoy, William Nicholls: Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. DAC 2001: 714-719
	1999
18		Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking: A Robust Solution to the Timing Convergence Problem in High-Performance Design. ICCD 1999: 250-257
	1997
17		Ramsey W. Haddad, Lukas P. P. P. van Ginneken, Narendra V. Shenoy: Discrete Drive Selection for Continuous Sizing. ICCD 1997: 110-115
16		Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy: The future of logic synthesis and physical design in deep-submicron process geometries. ISPD 1997: 218-224
15		Narendra V. Shenoy: Retiming: Theory and practice. Integration 22(1-2): 1-21 (1997)
	1996
14		Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy: Embedded tutorial: Speed - new paradigms in design for performance. ICCAD 1996: 700
	1995
13		Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Functional clock schedule optimization. VLSI Design 1995: 93-98
	1994
12		Narendra V. Shenoy, Richard L. Rudell: Efficient implementation of retiming. ICCAD 1994: 226-233
11		Luciano Lavagno, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli: Linear programming for hazard elimination in asynchronous circuits. VLSI Signal Processing 7(1-2): 137-160 (1994)
	1993
10		Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli: A Verification Technique for Gated Clock. DAC 1993: 123-127
9		Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Resynthesis of Multi-Phase Pipelines. DAC 1993: 490-496
8		Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Minimum padding to satisfy short path constraints. ICCAD 1993: 156-161
	1992
7		Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: On the Temporal Equivalence of Sequential Circuits. DAC 1992: 405-409
6		Thomas G. Szymanski, Narendra V. Shenoy: Verifying clock schedules. ICCAD 1992: 124-131
5		Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Graph algorithms for clock schedule optimization. ICCAD 1992: 132-136
	1991
4		Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Improved Logic Synthesis Algorithms for Table Look Up Architectures. ICCAD 1991: 564-567
3		Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. ICCAD 1991: 572-575
2		Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Retiming of Circuits with Single Phase Transparent Latches. ICCD 1991: 86-89
	1990
1		Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Logic Synthesis for Programmable Gate Arrays. DAC 1990: 620-625

Coauthor Index

1	Shabbir H. Batterywala	[23] [25] [27] [33] [34] [35]
2	Sambuddha Bhattacharya	[34] [35]
3	Robert K. Brayton	[1] [2] [3] [4] [5] [7] [8] [9] [13]
4	Raul Camposano	[28]
5	Chi-Foon Chan	[26]
6	Robert F. Damiano	[18]
7	Lukas P. P. P. van Ginneken	[14] [17]
8	Ramsey W. Haddad	[17]
9	Deirdre Hanford	[26]
10	Kevin Harer	[18]
11	Mahesh A. Iyer	[18]
12	Jamil Kawa	[28]
13	Masamichi Kawarabayashi	[10]
14	Kurt Keutzer	[16]
15	Luciano Lavagno	[11]
16	Stan Y. Liao	[22]
17	Jianfeng Luo	[33]
18	Hi-Keung Tony Ma	[18] [34] [35]
19	Mahesh Mehendale	[26]
20	Rajeev Murgai	[1] [3] [4]
21	A. Richard Newton	[16]
22	William Nicholls	[19] [20] [21] [22] [23] [24]
23	Yoshihito Nishizaki	[1]
24	Ralph H. J. M. Otten	[14]
25	Jian Yue Pan	[26]
26	Subramanian Rajagopalan	[33] [34] [35]
27	Richard L. Rudell	[12]
28	Alexander Saldanha	[13]
29	Alberto L. Sangiovanni-Vincentelli	[1] [2] [3] [4] [5] [7] [8] [9] [10] [11] [13]
30	Kanwar Jit Singh	[7]
31	Debjit Sinha	[29] [30] [31] [32] [33]
32	Thomas G. Szymanski	[6]
33	Paul Thilking	[18]
34	A. Vasudevan	[26]
35	Shaojun Wei	[26]
36	Hai Zhou	[19] [20] [21] [23] [29] [30] [31] [32] [33]

Colors in the list of coauthors