Ming-Hwa Sheu

	2009
28		Shyue-Wen Yang, Ming-Hwa Sheu, Jun-Jie Lin, Chuang-Chun Hu, Tzu-Hsiung Chen, Shau-Yin Tseng: Parallel 3-Pixel Labeling Method and its Hardware Architecture Design. IAS 2009: 185-188
	2008
27		Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-chuan Wu: The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing. ISCAS 2008: 480-483
26		Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: Low Complexity Dual-Mode Pulse Generator Designs. IEICE Transactions 91-A(7): 1812-1815 (2008)
25		Su-Hon Lin, Ming-Hwa Sheu: Area-Time Efficient Modulo 2n - 1 Adder Design Using Hybrid Carry Selection. IEICE Transactions 91-D(2): 361-362 (2008)
24		Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang: Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1). IEICE Transactions 91-D(7): 2058-2060 (2008)
	2007
23		Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai: Fast Fair Crossbar Scheduler for On-chip Router. ISCAS 2007: 385-388
22		Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu: Low Power Multipliers Using Enhenced Row Bypassing Schemes. SiPS 2007: 136-141
21		Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen: Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. SiPS 2007: 142-145
20		Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei, Chishyan Liaw: A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information. IEICE Transactions 90-A(11): 2575-2583 (2007)
	2006
19		Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei: The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. APCCAS 2006: 1587-1590
18		Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin, Wen-Tsai Sheu: Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1). APCCAS 2006: 2020-2023
17		Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu: Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. APCCAS 2006: 594-597
16		Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Ming-che Chen: Film-to-Video Conversion with Scene Cut Detection. ICICIC (1) 2006: 285-289
15		Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho: A high speed and energy efficient full adder design using complementary & level restoring carry logic. ISCAS 2006
14		Chung-Chi Lin, Chih-Jen Wei, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw: The VLSI design of de-interlacing with scene change detection. ISCAS 2006
13		Yin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu: Automatic Generation of Programmable Parallel CRC & Scrambler Designs. SiPS 2006: 286-291
	2005
12		Shyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang P. Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu: VLSI architecture design for a fast parallel label assignment in binary image. ISCAS (3) 2005: 2393-2396
11		Hsien-Huang P. Wu, Ming-Hwa Sheu, Tung-Yu Yang: Directional interpolation for field-sequential stereoscopic video. ISCAS (3) 2005: 2879-2882
10		Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw: Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. PCM (1) 2005: 291-302
	2003
9		Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu: A Fast Additive Normalization Method for Exponential Computation. DSD 2003: 286-293
	2002
8		Ming-Hwa Sheu, Su-Hon Lin: Fast design approach for implementing the approximate squaring function. APCCAS (2) 2002: 25-29
	2001
7		Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu: VLSI architecture of extended in-place path metric update for Viterbi decoders. ISCAS (4) 2001: 206-209
6		Ming-Hwa Sheu, Ho En Liao, Shih Tsung Kan, Ming-Der Shieh: A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. ISCAS (4) 2001: 446-449
5		Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo: A Systematic Approach for Parallel CRC Computations. J. Inf. Sci. Eng. 17(3): 445-461 (2001)
	2000
4		Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu: High-speed generation of LFSR signatures. Asian Test Symposium 2000: 222-
	1999
3		Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu: A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. ISCAS (1) 1999: 500-503
	1993
2		Ming-Hwa Sheu, Jhing-Fa Wang, Jau-Yien Lee, Lian-Ying Liu: An Expandable Chip Desing for Gray-scale Morphological Operations. ISCAS 1993: 1563-1566
1		Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu: A High Throughput-Rate Architecture for 8*8 2-D DCT. ISCAS 1993: 1578-1590

Coauthor Index

1	Chichyang Chen	[9]
2	Chung-Ho Chen	[5]
3	Jiun-Yan Chen	[13]
4	Ming-che Chen	[16]
5	Rui-Lin Chen	[9]
6	Si-Ying Chen	[21]
7	Tzu-Hsiung Chen	[28]
8	Huann-Keng Chiang	[10] [14] [16] [19] [20] [27]
9	Hung-En Chien	[12]
10	Cheng-Che Ho	[15]
11	Chuang-Chun Hu	[28]
12	Yin-Tsung Hwang	[13] [15] [17] [22] [26]
13	Shih Tsung Kan	[6]
14	Jau-Yien Lee	[1] [2]
15	Ho En Liao	[6]
16	Chishyan Liaw	[10] [14] [16] [20] [27]
17	Chih-Chieh Lin	[23]
18	Chung-Chi Lin	[10] [14] [16] [19] [20] [27]
19	Jin-Fa Lin	[15] [17] [22] [26]
20	Jing-Shiun Lin	[18]
21	Jun-Jie Lin	[28]
22	Su-Hon Lin	[8] [18] [21] [24] [25]
23	Lian-Ying Liu	[1] [2]
24	Hsin-Fu Lo	[4] [5]
25	Chia-Jen Sheu	[17] [22]
26	Jia-Lin Sheu	[3]
27	Wen-Tsai Sheu	[18]
28	Ming-Der Shieh	[3] [4] [5] [6] [7]
29	An-Nan Suen	[1]
30	Wen-Kai Tsai	[23]
31	Shau-Yin Tseng	[28]
32	Chao-Hsiang Wang	[24]
33	Jhing-Fa Wang	[1] [2]
34	Kuang-Hui Wang	[21]
35	Chih-Jen Wei	[14] [19] [20]
36	Chih-Yuen Wen	[23]
37	Ping-Kuo Weng	[12]
38	Che-Han Wu	[3]
39	Chien-Hsing Wu	[3] [7]
40	Chien-Ming Wu	[7]
41	Hsien-Huang P. Wu	[11] [12]
42	Ying-Yih Wu	[12]
43	Zeng-chuan Wu	[27]
44	Shyue-Wen Yang	[12] [23] [28]
45	Tung-Yu Yang	[11]
46	Chun-Kai Yeh	[23]
47	Jun-Jie Zhu	[21]

Colors in the list of coauthors