Ming-Der Shieh

	2009
30		Chia-Cheng Lo, Jung-Guan Luo, Ming-Der Shieh: Hardware/Software Codesign of Resource Constrained Real-Time Systems. IAS 2009: 177-180
29		Chia-Cheng Lo, Ying-Jhong Zeng, Ming-Der Shieh: Design of a High-Throughput CABAC Encoder. IEICE Transactions 92-D(4): 681-688 (2009)
	2008
28		Wen-Ching Lin, Jun-Hong Chen, Ming-Der Shieh: A new look-up table-based multiplier/squarer design for cryptosystems over GF(2m). ISCAS 2008: 464-467
27		Jun-Hong Chen, Wen-Ching Lin, Hao-Hsuan Wu, Ming-Der Shieh: High-speed modular multiplication design for public-key cryptosystems. ISCAS 2008: 680-683
26		Ming-Der Shieh, Jun-Hong Chen, Hao-Hsuan Wu, Wen-Ching Lin: A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem. IEEE Trans. VLSI Syst. 16(9): 1151-1161 (2008)
25		Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu: Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders. IEICE Transactions 91-D(9): 2300-2311 (2008)
	2007
24		Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin: A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem. ISCAS 2007: 3780-3783
	2006
23		Jun-Hong Chen, Ming-Der Shieh, Haw-Shiuan Wu, Wen-Ching Lin: Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation. APCCAS 2006: 606-609
22		Ming-Der Shieh, Yung-Kuei Lu, Shen-Ming Chung, Jun-Hong Chen: Design and implementation of efficient Reed-Solomon decoders for multi-mode applications. ISCAS 2006
21		Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang: Efficient path metric access for reducing interconnect overhead in Viterbi decoders. ISCAS 2006
20		Jing-Shiun Lin, Chung-Kung Lee, Ming-Der Shieh, Jun-Hong Chen: High-speed CRC design for 10 Gbps applications. ISCAS 2006
19		Ming-Der Shieh, Jun-Hong Chen, Chien-Ming Wu: High-Speed Design of Montgomery Inverse Algorithm over GF(2m). IEICE Transactions 89-A(2): 559-565 (2006)
	2005
18		Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu: Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography. ISCAS (5) 2005: 5254-5257
17		Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen: VLSI architectural design tradeoffs for sliding-window log-MAP decoders. IEEE Trans. VLSI Syst. 13(4): 439-447 (2005)
	2004
16		Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo: VLSI architecture exploration for sliding-window Log-MAP decoders. ISCAS (2) 2004: 513-516
15		Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). IEEE Trans. Computers 53(3): 375-380 (2004)
	2003
14		Chien-Ming Wu, Ming-Der Shieh, Hsin-Fu Lo, Min-Hsiung Hu: Implementation of channel demodulator for DAB system. ISCAS (2) 2003: 137-140
	2002
13		Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu: Memory arrangements in turbo decoders using sliding-window BCJR algorithm. ISCAS (5) 2002: 557-560
12		Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: An area-efficient systolic division circuit over GF(2/sup m/) for secure communication. ISCAS (5) 2002: 733-736
	2001
11		Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu: VLSI architecture of extended in-place path metric update for Viterbi decoders. ISCAS (4) 2001: 206-209
10		Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. ISCAS (4) 2001: 33-36
9		Ming-Hwa Sheu, Ho En Liao, Shih Tsung Kan, Ming-Der Shieh: A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. ISCAS (4) 2001: 446-449
8		Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu: Design of an efficient FFT processor for DAB system. ISCAS (4) 2001: 654-657
7		Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo: A Systematic Approach for Parallel CRC Computations. J. Inf. Sci. Eng. 17(3): 445-461 (2001)
	2000
6		Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu: High-speed generation of LFSR signatures. Asian Test Symposium 2000: 222-
	1999
5		Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu: A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. ISCAS (1) 1999: 500-503
4		Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu: An area-efficient versatile Reed-Solomon decoder for ADSL. ISCAS (1) 1999: 517-520
	1998
3		Chin-Long Wey, Ming-Der Shieh: Design of a High-Speed Square Generator. IEEE Trans. Computers 47(9): 1021-1026 (1998)
	1996
2		Chie Dou, Ming-Der Shieh: A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management. ICCD 1996: 149-
	1993
1		Chin-Long Wey, Ming-Der Shieh, P. David Fisher: ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits. ICCD 1993: 159-162

Coauthor Index

1	Chung-Ho Chen	[7]
2	Jun-Hong Chen	[16] [17] [18] [19] [20] [22] [23] [24] [26] [27] [28]
3	Shen-Ming Chung	[22]
4	Chie Dou	[2]
5	P. David Fisher	[1]
6	Min-Hsiung Hu	[14]
7	Chun-Ming Huang	[21]
8	Jin-Chuan Huang	[4]
9	Yin-Tsung Hwang	[10] [12] [15] [16] [17]
10	Shih Tsung Kan	[9]
11	Chung-Kung Lee	[20]
12	Ho En Liao	[9]
13	Jing-Shiun Lin	[20]
14	Wen-Ching Lin	[23] [24] [26] [27] [28]
15	Chia-Cheng Lo	[29] [30]
16	Hsin-Fu Lo	[6] [7] [8] [14] [16]
17	Yung-Kuei Lu	[22]
18	Jung-Guan Luo	[30]
19	Jia-Lin Sheu	[5]
20	Ming-Hwa Sheu	[5] [6] [7] [9] [11]
21	Tai-Ping Wang	[21] [25]
22	Chin-Long Wey	[1] [3]
23	Che-Han Wu	[5]
24	Chien-Hsing Wu	[4] [5] [10] [11] [12] [13] [15] [16] [17]
25	Chien-Ming Wu	[4] [8] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [21] [25]
26	Hao-Hsuan Wu	[26] [27]
27	Haw-Shiuan Wu	[23] [24]
28	Ying-Jhong Zeng	[29]

Colors in the list of coauthors