 | 2008 |
|---|
| 6 |       | Masanori Kurimoto,
Hiroaki Suzuki,
Rei Akiyama,
Tadao Yamanaka,
Haruyuki Ohkuma,
Hidehiro Takata,
Hirofumi Shinohara:
Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling.
DAC 2008: 884-889 |
| 5 | | Hiroaki Suzuki,
Masanori Kurimoto,
Tadao Yamanaka,
Hidehiro Takata,
Hiroshi Makino,
Hirofumi Shinohara:
Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology.
ISLPED 2008: 15-20 |
| 4 | | Masako Fujii,
Koji Nii,
Hiroshi Makino,
Shigeki Ohbayashi,
Motoshige Igarashi,
Takeshi Kawamura,
Miho Yokota,
Nobuhiro Tsuda,
Tomoaki Yoshizawa,
Toshikazu Tsutsui,
Naohiko Takeshita,
Naofumi Murata,
Tomohiro Tanaka,
Takanari Fujiwara,
Kyoko Asahina,
Masakazu Okada,
Kazuo Tomita,
Masahiko Takeuchi,
Shigehisa Yamamoto,
Hiromitsu Sugimoto,
Hirofumi Shinohara:
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology.
IEICE Transactions 91-C(8): 1338-1347 (2008) |
| 3 | | Hirofumi Shinohara,
Koji Nii,
Hidetoshi Onodera:
Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration.
IEICE Transactions 91-C(9): 1488-1500 (2008) |
| 2005 |
|---|
| 2 |  | Yasumasa Tsukamoto,
Koji Nii,
Susumu Imaoka,
Yuji Oda,
Shigeki Ohbayashi,
Tomoaki Yoshizawa,
Hiroshi Makino,
Koichiro Ishibashi,
Hirofumi Shinohara:
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
ICCAD 2005: 398-405 |
| 1993 |
|---|
| 1 | | Hiroshi Makino,
Yasunobu Nakase,
Hirofumi Shinohara:
A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture.
ICCD 1993: 202-205 |
