| 2012 | ||
|---|---|---|
| 65 | Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava: Design of an RNS reverse converter for a new five-moduli special set. ACM Great Lakes Symposium on VLSI 2012: 67-70 | |
| 2011 | ||
| 64 | Ke Bai, Aviral Shrivastava, Saleel Kudchadker: Stack data management for Limited Local Memory (LLM) multi-core processors. ASAP 2011: 231-234 | |
| 63 | Reiley Jeyapaul, Aviral Shrivastava: Smart cache cleaning: energy efficient vulnerability reduction in embedded processors. CASES 2011: 105-114 | |
| 62 | Ke Bai, Di Lu, Aviral Shrivastava: Vector class on limited local memory (LLM) multi-core processors. CASES 2011: 215-224 | |
| 61 | Jing Lu, Yooseong Kim, Aviral Shrivastava, Chuan Huang: Branch penalty reduction on IBM cell SPUs via software branch hinting. CODES+ISSS 2011: 355-364 | |
| 60 | Yooseong Kim, Aviral Shrivastava: CuMAPz: a tool to analyze memory access patterns in CUDA. DAC 2011: 128-133 | |
| 59 | Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula: Enabling Multithreading on CGRAs. ICPP 2011: 255-264 | |
| 58 | Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee: UnSync: A Soft Error Resilient Redundant Multicore Architecture. ICPP 2011: 632-641 | |
| 57 | Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava: Fast and energy-efficient constant-coefficient FIR filters using residue number system. ISLPED 2011: 385-390 | |
| 56 | Aarul Jain, Aviral Shrivastava, Chaitali Chakrabarti: LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches. VLSI Design 2011: 298-303 | |
| 55 | Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunheung Paek: Memory access optimization in compilation for coarse-grained reconfigurable architectures. ACM Trans. Design Autom. Electr. Syst. 16(4): 42 (2011) | |
| 54 | Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Doosan Cho, Yunheung Paek: High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1599-1609 (2011) | |
| 53 | Jongeun Lee, Aviral Shrivastava: Static Analysis of Register File Vulnerability. IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 607-616 (2011) | |
| 2010 | ||
| 52 | Seung Chul Jung, Aviral Shrivastava, Ke Bai: Dynamic code mapping for limited local memory systems. ASAP 2010: 13-20 | |
| 51 | Tom Vander Aa, Praveen Raghavan, Scott A. Mahlke, Bjorn De Sutter, Aviral Shrivastava, Frank Hannig: Compilation techniques for CGRAs: exploring all parallelization approaches. CODES+ISSS 2010: 185-186 | |
| 50 | Ke Bai, Aviral Shrivastava: Heap data management for limited local memory (LLM) multi-core processors. CODES+ISSS 2010: 317-326 | |
| 49 | Jeffrey Boyd, Hari Sundaram, Aviral Shrivastava: Power-accuracy tradeoffs in human activity transition detection. DATE 2010: 1524-1529 | |
| 48 | Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Yunheung Paek: Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays. HiPEAC 2010: 171-185 | |
| 47 | Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul: Cache vulnerability equations for protecting data in embedded processor caches from soft errors. LCTES 2010: 143-152 | |
| 46 | Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunheung Paek: Operation and data mapping for CGRAs with multi-bank memory. LCTES 2010: 17-26 | |
| 45 | Reiley Jeyapaul, Aviral Shrivastava: B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems. SCOPES 2010: 2 | |
| 44 | Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian: Partitioning techniques for partially protected caches in resource-constrained embedded systems. ACM Trans. Design Autom. Electr. Syst. 15(4): (2010) | |
| 43 | Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. IEEE Trans. VLSI Syst. 18(6): 988-997 (2010) | |
| 42 | Jongeun Lee, Aviral Shrivastava: A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1018-1027 (2010) | |
| 41 | Reiley Jeyapaul, Aviral Shrivastava: Code Transformations for TLB Power Reduction. International Journal of Parallel Programming 38(3-4): 254-276 (2010) | |
| 2009 | ||
| 40 | Arun Kannan, Aviral Shrivastava, Amit Pabalkar, Jongeun Lee: A software solution for dynamic stack management on scratch pad memory. ASP-DAC 2009: 612-617 | |
| 39 | Jongeun Lee, Aviral Shrivastava: Compiler-managed register file protection for energy-efficient soft error reduction. ASP-DAC 2009: 618-623 | |
| 38 | Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak: Exploiting residue number system for power-efficient digital signal processing in embedded processors. CASES 2009: 19-28 | |
| 37 | Jongeun Lee, Aviral Shrivastava: Static analysis to mitigate soft errors in register files. DATE 2009: 1367-1372 | |
| 36 | Sai Krishna Mylavarapu, Siddharth Choudhuri, Aviral Shrivastava, Jongeun Lee, Tony Givargis: FSAF: File system aware flash translation layer for NAND Flash Memories. DATE 2009: 399-404 | |
| 35 | Jongeun Lee, Aviral Shrivastava: A compiler optimization to reduce soft errors in register files. LCTES 2009: 41-49 | |
| 34 | Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava: Code Transformations for TLB Power Reduction. VLSI Design 2009: 413-418 | |
| 33 | Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Yunheung Paek: A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures. IEEE Trans. VLSI Syst. 17(11): 1565-1578 (2009) | |
| 32 | Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian: Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications. IEEE Trans. VLSI Syst. 17(9): 1343-1347 (2009) | |
| 31 | Aviral Shrivastava, Arun Kannan, Jongeun Lee: A Software-Only Solution to Use Scratch Pads for Stack Data. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1719-1727 (2009) | |
| 30 | Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Sanghyun Park, Yunheung Paek: Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 461-465 (2009) | |
| 2008 | ||
| 29 | Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian: Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach. ACM Multimedia 2008: 319-328 | |
| 28 | Aviral Shrivastava, Ilya Issenin, Nikil Dutt: A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. ASP-DAC 2008: 328-333 | |
| 27 | Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek: SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. ASP-DAC 2008: 776-782 | |
| 26 | Jongeun Lee, Aviral Shrivastava: Static analysis of processor stall cycle aggregation. CODES+ISSS 2008: 25-30 | |
| 25 | Sanghyun Park, Aviral Shrivastava, Yunheung Paek: Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors. DATE 2008: 1190-1195 | |
| 24 | Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian: Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures. DIPES 2008: 213-225 | |
| 23 | Amit Pabalkar, Aviral Shrivastava, Arun Kannan, Jongeun Lee: SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories. HiPC 2008: 569-582 | |
| 22 | Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi: PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. VLSI Design 2008: 421-427 | |
| 21 | Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design 2008: 515-520 | |
| 20 | Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design 2008: 533-539 | |
| 19 | Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie: Register File Power Reduction Using Bypass Sensitive Compiler. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1155-1159 (2008) | |
| 2007 | ||
| 18 | Michael A. Baker, Aviral Shrivastava, Karam S. Chatha: Smart driver for power reduction in next generation bistable electrophoretic display technology. CODES+ISSS 2007: 197-202 | |
| 17 | Qiang Zhu, Aviral Shrivastava, Nikil Dutt: Interactive presentation: Functional and timing validation of partially bypassed processor pipelines. DATE 2007: 1164-1169 | |
| 16 | Satyajayant Misra, Guoliang Xue, Aviral Shrivastava: Robust Localization in Wireless Sensor Networks through the Revocation of Malicious Anchors. ICC 2007: 3057-3062 | |
| 15 | Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek: Automatic Design Space Exploration of Register Bypasses in Embedded Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2102-2115 (2007) | |
| 2006 | ||
| 14 | Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian: Mitigating soft error failures for multimedia applications by selective data protection. CASES 2006: 411-420 | |
| 13 | Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil Dutt, Yunheung Paek: Automatic generation of operation tables for fast exploration of bypasses in embedded processors. DATE 2006: 1197-1202 | |
| 12 | Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie: Bypass aware instruction scheduling for register file power reduction. LCTES 2006: 173-181 | |
| 11 | Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau: Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). ACM Trans. Design Autom. Electr. Syst. 11(1): 123-146 (2006) | |
| 10 | Prabhat Mishra, Aviral Shrivastava, Nikil Dutt: Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. ACM Trans. Design Autom. Electr. Syst. 11(3): 626-658 (2006) | |
| 9 | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Retargetable pipeline hazard detection for partially bypassed processors. IEEE Trans. VLSI Syst. 14(8): 791-801 (2006) | |
| 2005 | ||
| 8 | Aviral Shrivastava, Ilya Issenin, Nikil Dutt: Compilation techniques for energy reduction in horizontally partitioned cache architectures. CASES 2005: 90-96 | |
| 7 | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Aggregating processor free time for energy reduction. CODES+ISSS 2005: 154-159 | |
| 6 | Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie: PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors. DATE 2005: 1264-1269 | |
| 2004 | ||
| 5 | Aviral Shrivastava, Nikil D. Dutt: Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA). ASP-DAC 2004: 475-477 | |
| 4 | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Operation tables for scheduling in the presence of incomplete bypassing. CODES+ISSS 2004: 194-199 | |
| 2002 | ||
| 3 | Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau: An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. DATE 2002: 402-408 | |
| 2 | Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi: A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design . ISSS 2002: 120-125 | |
| 2000 | ||
| 1 | Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan: Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. VLSI Design 2000: 110-113 | |
Colors in the list of coauthors
Last update Fri May 25 01:42:58 2012 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page