| 2006 |
|---|
| 6 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.
IEEE Trans. VLSI Syst. 14(11): 1203-1215 (2006) |
| 2005 |
|---|
| 5 | | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Testing Superscalar Processors in Functional Mode.
FPL 2005: 747-750 |
| 4 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Instruction-based delay fault self-testing of pipelined processor cores.
ISCAS (6) 2005: 5686-5689 |
| 3 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Delay Fault Testing of Processor Cores in Functional Mode.
IEICE Transactions 88-D(3): 610-618 (2005) |
| 2004 |
|---|
| 2 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Instruction-Based Delay Fault Self-Testing of Processor Cores.
VLSI Design 2004: 933- |
| 2003 |
|---|
| 1 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Software-Based Delay Fault Testing of Processor Cores.
Asian Test Symposium 2003: 68-71 |
