 | 2009 |
|---|
| 5 |       | Roopak Sinha,
Partha S. Roop,
Samik Basu,
Zoran Salcic:
Multi-clock Soc design using protocol conversion.
DATE 2009: 123-128 |
| 2008 |
|---|
| 4 | | Roopak Sinha,
Partha S. Roop,
Samik Basu:
A Module Checking Based Converter Synthesis Approach for SoCs.
VLSI Design 2008: 492-501 |
| 3 | | Roopak Sinha,
Partha S. Roop,
Samik Basu:
A Model Checking Approach to Protocol Conversion.
Electr. Notes Theor. Comput. Sci. 203(4): 81-94 (2008) |
| 2007 |
|---|
| 2 | | Samik Basu,
Partha S. Roop,
Roopak Sinha:
Local Module Checking for CTL Specifications.
Electr. Notes Theor. Comput. Sci. 176(2): 125-141 (2007) |
| 2005 |
|---|
| 1 | | Roopak Sinha,
Partha S. Roop,
Bakhadyr Khoussainov:
Adaptive Verification using Forced Simulation.
Electr. Notes Theor. Comput. Sci. 141(3): 171-197 (2005) |
