S. C. Smith

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2006

2 S. C. Smith: Speedup of NULL convention digital circuits using NULL cycle reduction. Journal of Systems Architecture 52(7): 411-422 (2006)

2005

1 S. C. Smith: Development of a large word-width high-speed asynchronous multiply and accumulate unit. Integration 39(1): 12-28 (2005)

	2006
2		S. C. Smith: Speedup of NULL convention digital circuits using NULL cycle reduction. Journal of Systems Architecture 52(7): 411-422 (2006)
	2005
1		S. C. Smith: Development of a large word-width high-speed asynchronous multiply and accumulate unit. Integration 39(1): 12-28 (2005)