Scott C. Smith

	2009
17		Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia Di: Delay-Insensitive Ternary Logic. CDES 2009: 3-0
	2007
16		Scott C. Smith: Design of a logic element for implementing an asynchronous FPGA. FPGA 2007: 13-22
15		Venkat Satagopan, Bonita Bhaskaran, Waleed Al-Assadi, Scott C. Smith, Sindhu Kakarla: DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. IEEE Trans. VLSI Syst. 15(10): 1155-1159 (2007)
14		Scott C. Smith: Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. IEEE Trans. VLSI Syst. 15(6): 672-683 (2007)
13		Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, Scott C. Smith: Automated energy calculation and estimation for delay-insensitive digital circuits. Microelectronics Journal 38(10-11): 1095-1107 (2007)
	2005
12		Anshul Singh, Scott C. Smith: Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. CDES 2005: 115-121
11		Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith: High-Speed Energy Estimation for Delay-Insensitive Circuits. CDES 2005: 35-41
10		Bonita Bhaskaran, Venkat Satagopan, Waleed Al-Assadi, Scott C. Smith: Implementation of Design For Test for Asynchronous NCL Designs. CDES 2005: 78-84
	2004
9		Scott C. Smith: Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput. ESA/VLSI 2004: 407-412
8		Scott C. Smith: Design of a NULL Convention Self-Timed Divider. ESA/VLSI 2004: 447-453
7		Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, D. Ferguson, D. Lamb: Optimization of NULL convention self-timed circuits. Integration 37(3): 135-165 (2004)
	2003
6		Scott C. Smith: Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy. VLSI 2003: 143-149
5		Satish K. Bandapati, Scott C. Smith: Design and Characterization of NULL Convention Arithmetic Logic Units. VLSI 2003: 178-184
4		Satish K. Bandapati, Scott C. Smith, Minsu Choi: Design and Characterization of Null Convention Self-Timed Multipliers. IEEE Design & Test of Computers 20(6): 26-36 (2003)
	2002
3		Scott C. Smith: Speedup of Self-Timed Digital Systems Using Early Completion. ISVLSI 2002: 107-116
2		Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, M. Hagedorn, D. Ferguson: NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation. Journal of Systems Architecture 47(12): 977-998 (2002)
	2001
1		Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, M. Hagedorn, D. Ferguson: Delay-insensitive gate-level pipelining. Integration 30(2): 103-131 (2001)

Coauthor Index

1	Waleed Al-Assadi	[10] [15]
2	Satish K. Bandapati	[4] [5]
3	Bonita Bhaskaran	[10] [11] [13] [15]
4	Minsu Choi	[4]
5	Ronald F. DeMara	[1] [2] [7]
6	Jia Di	[17]
7	D. Ferguson	[1] [2] [7]
8	M. Hagedorn	[1] [2]
9	Sindhu Kakarla	[15]
10	D. Lamb	[7]
11	Ravi Sankar Parameswaran Nair	[17]
12	Venkat Satagopan	[10] [11] [13] [15]
13	Anshul Singh	[12] [13]
14	Jiann S. Yuan	[1] [2] [7]

Colors in the list of coauthors