 | 2009 |
|---|
| 6 |       | Victor Lomné,
Philippe Maurine,
Lionel Torres,
Michel Robert,
Rafael Soares,
Ney Calazans:
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA.
DATE 2009: 634-639 |
| 2008 |
|---|
| 5 | | Julian J. H. Pontes,
Matheus T. Moreira,
Rafael Soares,
Ney Laert Vilar Calazans:
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques.
ISVLSI 2008: 347-352 |
| 4 | | Rafael Soares,
Ney Laert Vilar Calazans,
Victor Lomné,
Philippe Maurine,
Lionel Torres,
Michel Robert:
Evaluating the robustness of secure triple track logic through prototyping.
SBCCI 2008: 193-198 |
| 2007 |
|---|
| 3 | | Julian J. H. Pontes,
Rafael Soares,
Ewerson Carvalho,
Fernando Moraes,
Ney Calazans:
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros.
ICCD 2007: 541-546 |
| 2 |  | Leandro Möller,
Ismael Grehs,
Ewerson Carvalho,
Rafael Soares,
Ney Calazans,
Fernando Moraes:
A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems.
ReCoSoC 2007: 23-30 |
| 2006 |
|---|
| 1 | | Leandro Möller,
Rafael Soares,
Ewerson Carvalho,
Ismael Grehs,
Ney Calazans,
Fernando Moraes:
Infrastructure for dynamic reconfigurable systems: choices and trade-offs.
SBCCI 2006: 44-49 |
