Dinesh Somasekhar

	2007
14		Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy: Fine-Grained Redundancy in Adders. ISQED 2007: 317-321
	2006
13		Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De: Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. ISCAS 2006
	2002
12		Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy: Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. VLSI Syst. 10(1): 1-5 (2002)
11		Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy: Skewed CMOS: noise-tolerant high-performance low-power static circuit family. IEEE Trans. VLSI Syst. 10(4): 469-476 (2002)
	2000
10		Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De: Dynamic noise analysis in precharge-evaluate circuits. DAC 2000: 243
9		Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar: Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD 2000: 241-246
	1999
8		Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy: Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. DAC 1999: 442-445
7		Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy: Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. ICCD 1999: 230-235
6		Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy: Models and algorithms for bounds on leakage in CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 714-725 (1999)
	1998
5		Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy: IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. Great Lakes Symposium on VLSI 1998: 243-248
4		Dinesh Somasekhar, Kaushik Roy: LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. IEEE Trans. VLSI Syst. 6(4): 573-577 (1998)
	1997
3		Dinesh Somasekhar, Kaushik Roy: LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. ISLPED 1997: 18-23
	1993
2		Dinesh Somasekhar, V. Visvanathan: A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. VLSI Design 1993: 347-350
1		Dinesh Somasekhar, V. Visvanathan: A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. IEEE Trans. VLSI Syst. 1(4): 415-422 (1993)

Coauthor Index

1	Lih-Yih Chiou	[12]
2	Seung Hoon Choi	[10]
3	Vivek De	[10] [13]
4	Mark C. Johnson	[6] [8] [12]
5	Muhammad M. Khellah	[13]
6	Cheng-Kok Koh	[9]
7	Shih-Lien Lu	[14]
8	Khurram Muhammad	[7]
9	Patrick Ndai	[14]
10	Kaushik Roy	[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14]
11	Naran Sirisantana	[11]
12	Hendrawan Soeleman	[5]
13	Alexandre Solomatnikov	[9] [11]
14	V. Visvanathan	[1] [2]
15	Yibin Ye	[10] [13]

Colors in the list of coauthors