Alberto Ferreira de Souza

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2008
9EEAlberto Ferreira de Souza, Rajkumar Buyya: Introduction to the Special Issue on the 18th International Symposium on Computer Architecture and High Performance Computing. International Journal of Parallel Programming 36(2): 163-165 (2008)
8EEPeter Rounce, Alberto Ferreira de Souza: Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture. International Journal of Parallel Programming 36(2): 184-205 (2008)
2006
7EEPeter Rounce, Alberto Ferreira de Souza: The mDTSVLIW: a Multi-Threaded Trace-based VLIW Architecture. SBAC-PAD 2006: 63-72
2000
6EEAlberto Ferreira de Souza, Peter Rounce: On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture. IPDPS 2000: 565-572
5EEAlberto Ferreira de Souza, Peter Rounce: Dynamically Scheduling VLIW Instructions. J. Parallel Distrib. Comput. 60(12): 1480-1511 (2000)
1999
4 Alberto Ferreira de Souza, Peter Rounce: Effect of Multicycle Intructions on the Integer Performance of the Dynamixcally Trace Scheduled VLIW Architecture. HPCN Europe 1999: 1203-1206
3EEAlberto Ferreira de Souza, Peter Rounce: Dynamically Scheduling the Trace Produced During Program Execution into VLIW Instructions. IPPS/SPDP 1999: 248-257
1998
2 Alberto Ferreira de Souza, Peter Rounce: Dynamically Trace Scheduled VLIW Architectures. HPCN Europe 1998: 993-995
1997
1 Alberto Ferreira de Souza, Edil S. Tavares Fernandes, Andrew Wolfe: On the balance of VLIW architectures. Journal of Systems Architecture 43(1-5): 15-22 (1997)

Coauthor Index

1Rajkumar Buyya [9]
2Edil S. Tavares Fernandes [1]
3Peter Rounce [2] [3] [4] [5] [6] [7] [8]
4Andrew Wolfe [1]

Colors in the list of coauthors

Copyright © Fri Oct 3 18:41:27 2008 by Michael Ley (ley@uni-trier.de)