Jens Sparsø

	2009
18		Matthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø: Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip. CODES+ISSS 2009: 481-490
	2008
17		Mikkel Bystrup Stensgaard, Jens Sparsø: ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. NOCS 2008: 55-64
16		Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen: A Reactive and Cycle-True IP Emulator for MPSoC Exploration. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 109-122 (2008)
	2007
15		Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø: A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. DATE 2007: 648-653
	2006
14		Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen: A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. DSD 2006: 641-648
13		Tobias Bjerregaard, Jens Sparsø: Packetizing OCP Transactions in the MANGO Network-on-Chip. DSD 2006: 657-664
	2005
12		Tobias Bjerregaard, Jens Sparsø: A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip. ASYNC 2005: 34-43
11		Tobias Bjerregaard, Jens Sparsø: A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. DATE 2005: 1226-1231
10		Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø, Jan Madsen: A Network Traffic Generator Model for Fast Network-on-Chip Simulation. DATE 2005: 780-785
9		Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen: A Traffic Injection Methodology with Support for System-Level Synchronization. VLSI-SoC 2005: 145-161
	2004
8		S. F. Nielsen, Jens Sparsø, Jan Madsen: Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. DSD 2004: 298-305
7		Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø: A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling. PATMOS 2004: 301-310
6		Özgün Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen: A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing. VLSI Signal Processing 37(1): 95-110 (2004)
	2002
5		Vojin G. Oklobdzija, Jens Sparsø: Future directions in clocking multi-ghz systems. ISLPED 2002: 219
	1998
4		Kåre T. Christensen, Peter Jensen, Peter Korger, Jens Sparsø: The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. ASYNC 1998: 108-
	1994
3		Lars Skovby Nielsen, C. Niessen, Jens Sparsø, Kees van Berkel: Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. IEEE Trans. VLSI Syst. 2(4): 391-397 (1994)
	1993
2		Jens Sparsø, Christian D. Nielsen, Lars Skovby Nielsen, Jørgen Staunstrup: Design of Self-timed Multipliers: A Comparison. Asynchronous Design Methodologies 1993: 165-179
	1991
1		Jens Sparsø, Steen Pedersen, Erik Paaske: Design of a Fully Parallel Viterbi Decoder. VLSI 1991: 29-38

Coauthor Index

1	Federico Angiolini	[9] [10] [16]
2	Luca Benini	[9] [16]
3	Kees van Berkel	[3]
4	Tobias Bjerregaard	[7] [11] [12] [13] [14] [15]
5	Kåre T. Christensen	[4]
6	Niels Haandbæk	[6]
7	Mogens Isager	[6]
8	Peter Jensen	[4]
9	Peter Korger	[4]
10	Jan Madsen	[8] [9] [10] [16]
11	Shankar Mahadevan	[7] [9] [10] [16]
12	Christian D. Nielsen	[2]
13	Lars Skovby Nielsen	[2] [3] [6]
14	S. F. Nielsen	[8]
15	C. Niessen	[3]
16	Vojin G. Oklobdzija	[5]
17	Rasmus Grøndahl Olsen	[10]
18	Erik Paaske	[1]
19	Özgün Paker	[6]
20	Johnny Halkjær Pedersen	[14]
21	Steen Pedersen	[1]
22	Jørgen Staunstrup	[2]
23	Mikkel Bystrup Stensgaard	[14] [15] [17] [18]
24	Michael Storgaard	[10]
25	Matthias Bo Stuart	[18]

Colors in the list of coauthors