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12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy: A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. VLSI Design 2009: 301-306
2008
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari: Toward Increasing FPGA Lifetime. IEEE Trans. Dependable Sec. Comput. 5(2): 115-127 (2008)
2007
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan: FPGA routing architecture analysis under variations. ICCD 2007: 152-157
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKin Wah Fung, Olivier Bodenreider, Alan R. Aronson, William T. Hole, Suresh Srinivasan: Combining Lexical and Semantic Methods of Inter-terminology Mapping Using the UMLS. MedInfo 2007: 605-609
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAman Gayasen, Suresh Srinivasan, Narayanan Vijaykrishnan, Mahmut T. Kandemir: Design of power-aware FPGA fabrics. IJES 3(1/2): 52-64 (2007)
2006
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLBalaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo: Leakage Optimized DECAP Design for FPGAs. APCCAS 2006: 960-963
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari: FLAW: FPGA lifetime awareness. DAC 2006: 630-635
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLIng-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada: Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED 2006: 775-780
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuresh Srinivasan, Narayanan Vijaykrishnan: Variation Aware Placement for FPGAs. ISVLSI 2006: 422-423
2005
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan: Leakage control in FPGA routing fabric. ASP-DAC 2005: 661-664
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuresh Srinivasan, Lin Li, Narayanan Vijaykrishnan: Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. DATE 2005: 218-223
2004
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Improving soft-error tolerance of FPGA configuration bits. ICCAD 2004: 107-110

Coauthor Index

1Alan R. Aronson [9]
2Olivier Bodenreider [9]
3Nagu R. Dhanwada [5]
4Vasantha Erraguntla [12]
5Kin Wah Fung [9]
6Aman Gayasen [1] [3] [8]
7William T. Hole [9]
8Mary Jane Irwin [1] [11]
9Mahmut T. Kandemir [1] [8]
10Ram Krishnamurthy [12]
11Lin Li [2]
12Ing-Chao Lin [5]
13Rong Luo [7]
14Prasanth Mangalagiri [6] [10] [11]
15Sanu Mathew [12]
16Krishnan Ramakrishnan [11]
17Karthik Sarpatwari [6] [11]
18Tim Tuan [3]
19Balaji Vaidyanathan [7]
20Narayanan Vijaykrishnan (Vijaykrishnan Narayanan) [1] [2] [3] [4] [5] [6] [7] [8] [10] [11]
21Yuan Xie [1] [6] [7] [10] [11]

Colors in the list of coauthors

Copyright © Wed Nov 25 14:46:41 2009 by Michael Ley (ley@uni-trier.de)