 | 2000 |
|---|
| 17 |       | Charles H. Stapper:
LSI yield modeling and process monitoring.
IBM Journal of Research and Development 44(1): 112-118 (2000) |
| 1995 |
|---|
| 16 |  | Wayne F. Ellis,
John E. Barth Jr.,
Sri Divakaruni,
Jeffrey Dreibelbis,
Anatol Furman,
Erik L. Hedberg,
Hsing-San Lee,
Thomas M. Maffitt,
Christopher P. Miller,
Charles H. Stapper,
Howard L. Kalter:
Multipurpose DRAM architecture for optimal power, performance, and product flexibility.
IBM Journal of Research and Development 39(1-2): 51-62 (1995) |
| 1994 |
|---|
| 15 | | Charles H. Stapper,
A. J. Rideout:
On Fractal Yield Models: A Statistical Paradox.
DFT 1994: 83-87 |
| 14 | | Israel Koren,
Zahava Koren,
Charles H. Stapper:
A statistical study of defect maps of large area VLSI IC's.
IEEE Trans. VLSI Syst. 2(2): 249-256 (1994) |
| 1993 |
|---|
| 13 | | Charles H. Stapper,
J. A. Patrick,
R. J. Rosner:
Yield Model for ASIC and Processor Chips.
DFT 1993: 136-143 |
| 12 | | Israel Koren,
Zahava Koren,
Charles H. Stapper:
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits.
IEEE Trans. Computers 42(6): 724-734 (1993) |
| 11 | | Charles H. Stapper:
Improved Yield Models for Fault-Tolerant Memory Chips.
IEEE Trans. Computers 42(7): 872-881 (1993) |
| 1992 |
|---|
| 10 | | Charles H. Stapper:
A New Statistical Approach for Fault-Tolerant VLSI Systems.
FTCS 1992: 356-365 |
| 9 | | Charles H. Stapper,
Hsing-San Lee:
Synergistic Fault-Tolerance for Memory Chips.
IEEE Trans. Computers 41(9): 1078-1087 (1992) |
| 1991 |
|---|
| 8 | | Charles H. Stapper:
Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 399-406 (1991) |
| 1989 |
|---|
| 7 | | Charles H. Stapper:
Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review.
IBM Journal of Research and Development 33(2): 162-173 (1989) |
| 6 | | Charles H. Stapper:
Simulation of spatial fault distributions for integrated circuit yield estimations.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(12): 1314-1318 (1989) |
| 1986 |
|---|
| 5 | | Andrzej J. Strojwas,
Clark Beck,
Dennis Buss,
Tülin Erdim Mangir,
Charles H. Stapper:
Yield of VLSI circuits: myths vs. reality (panel).
DAC 1986: 234-235 |
| 1984 |
|---|
| 4 | | Charles H. Stapper:
Modeling of Defects in Integrated Circuit Photolithographic Patterns.
IBM Journal of Research and Development 28(4): 461-475 (1984) |
| 3 | | Charles H. Stapper:
Yield Model for Fault Clusters Within Integrated Circuits.
IBM Journal of Research and Development 28(5): 636-640 (1984) |
| 1983 |
|---|
| 2 | | Charles H. Stapper:
Modeling of Integrated Circuit Defect Sensitivities.
IBM Journal of Research and Development 27(6): 549-557 (1983) |
| 1976 |
|---|
| 1 | | Charles H. Stapper:
LSI Yield Modeling and Process Monitoring.
IBM Journal of Research and Development 20(3): 228-234 (1976) |
