 | 2009 |
| 21 |  | Sjoerd Meijer,
Hristo Nikolov,
Todor Stefanov:
On compile-time evaluation of process partitioning transformations for Kahn process networks.
CODES+ISSS 2009: 31-40 |
| 20 |  | Zubair Nawaz,
Thomas Marconi,
Koen Bertels,
Todor Stefanov:
Flexible pipelining design for recursive variable expansion.
IPDPS 2009: 1-8 |
| 19 |  | Dmitry Nadezhkin,
Sjoerd Meijer,
Todor Stefanov,
Ed F. Deprettere:
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell.
SAMOS 2009: 308-317 |
| 2008 |
| 18 |  | Hristo Nikolov,
Mark Thompson,
Todor Stefanov,
Andy D. Pimentel,
Simon Polstra,
R. Bose,
Claudiu Zissulescu,
Ed F. Deprettere:
Daedalus: toward composable multimedia MP-SoC design.
DAC 2008: 574-579 |
| 17 |  | Ozana Silvia Dragomir,
Todor Stefanov,
Koen Bertels:
Loop unrolling and shifting for reconfigurable architectures.
FPL 2008: 167-172 |
| 16 |  | Andy D. Pimentel,
Todor Stefanov,
Hristo Nikolov,
Mark Thompson,
Simon Polstra,
Ed F. Deprettere:
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study.
SAMOS 2008: 167-176 |
| 15 |  | Kamana Sigdel,
Mark Thompson,
Andy D. Pimentel,
Todor Stefanov,
Koen Bertels:
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures.
SAMOS 2008: 279-288 |
| 14 |  | Hristo Nikolov,
Todor Stefanov,
Ed F. Deprettere:
Systematic and Automated Multiprocessor System Design, Programming, and Implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 542-555 (2008) |
| 2007 |
| 13 |  | Jae Young Hur,
Todor Stefanov,
Stephan Wong,
Stamatis Vassiliadis:
Systematic Customization of On-Chip Crossbar Interconnects.
ARC 2007: 61-72 |
| 12 |  | Jae Young Hur,
Todor Stefanov,
Stephan Wong,
Stamatis Vassiliadis:
Customizing Reconfigurable On-Chip Crossbar Scheduler.
ASAP 2007: 210-215 |
| 11 |  | Mark Thompson,
Hristo Nikolov,
Todor Stefanov,
Andy D. Pimentel,
Cagkan Erbas,
Simon Polstra,
Ed F. Deprettere:
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs.
CODES+ISSS 2007: 9-14 |
| 10 |  | Hristo Nikolov,
Todor Stefanov,
Ed F. Deprettere:
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips.
FPL 2007: 580-584 |
| 2006 |
| 9 |  | Ed F. Deprettere,
Todor Stefanov,
Shuvra S. Bhattacharyya,
Mainak Sen:
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts.
ASAP 2006: 186-190 |
| 8 |  | Hristo Nikolov,
Todor Stefanov,
Ed F. Deprettere:
Multi-processor system design with ESPAM.
CODES+ISSS 2006: 211-216 |
| 7 |  | Hristo Nikolov,
Todor Stefanov,
Ed F. Deprettere:
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips.
FPL 2006: 1-6 |
| 2005 |
| 6 |  | Hristo Nikolov,
Todor Stefanov,
Ed F. Deprettere:
Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters.
FCCM 2005: 255-263 |
| 2004 |
| 5 |  | Todor Stefanov,
Claudiu Zissulescu,
Alexandru Turjan,
Bart Kienhuis,
Ed F. Deprettere:
System Design Using Kahn Process Networks: The Compaan/Laura Approach.
DATE 2004: 340-345 |
| 2003 |
| 4 |  | Todor Stefanov,
Ed F. Deprettere:
Deriving process networks from weakly dynamic applications in system-level design.
CODES+ISSS 2003: 90-96 |
| 3 |  | Claudiu Zissulescu,
Todor Stefanov,
Bart Kienhuis,
Ed F. Deprettere:
Laura: Leiden Architecture Research and Exploration Tool.
FPL 2003: 911-920 |
| 2002 |
| 2 |  | Todor Stefanov,
Bart Kienhuis,
Ed F. Deprettere:
Algorithmic transformation techniques for efficient exploration of alternative application instances.
CODES 2002: 7-12 |
| 2001 |
| 1 |  | Paul Lieverse,
Todor Stefanov,
Pieter van der Wolf,
Ed F. Deprettere:
System Level Design with Spade: an M-JPEG Case Study.
ICCAD 2001: 31-38 |