| 2009 | ||
|---|---|---|
| 25 | Leon Stok: From restrictive to prescriptive design. ASP-DAC 2009 | |
| 2008 | ||
| 24 | Leon Stok: Variability and New Design Paradigms. IEEE Design & Test of Computers 25(4): 344 (2008) | |
| 2007 | ||
| 23 | Sachin S. Sapatnekar, Leon Stok: DAC Highlights. IEEE Design & Test of Computers 24(5): 502-504 (2007) | |
| 2005 | ||
| 22 | Ruchir Puri, Leon Stok, Subhrajit Bhattacharya: Keeping hot chips cool. DAC 2005: 285-288 | |
| 21 | Ruchir Puri, David S. Kung, Leon Stok: Minimizing power with flexible voltage islands. ISCAS (1) 2005: 21-24 | |
| 2003 | ||
| 20 | Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793 | |
| 19 | Leon Stok, John M. Cohn: There is life left in ASICs. ISPD 2003: 48-50 | |
| 18 | Soha Hassoun, Steven M. Nowick, Leon Stok: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 662-664 (2003) | |
| 2002 | ||
| 17 | Thomas Kutzschebauch, Leon Stok: Layout Driven Decomposition with Congestion Consideration. DATE 2002: 672-676 | |
| 2001 | ||
| 16 | Thomas Kutzschebauch, Leon Stok: Congestion Aware Layout Driven Logic Synthesis. ICCAD 2001: 216-223 | |
| 2000 | ||
| 15 | Raul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten: Timing closure: the solution and its problems. ASP-DAC 2000: 359-364 | |
| 14 | Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty: Transformational Placement and Synthesis. DATE 2000: 194-201 | |
| 13 | Thomas Kutzschebauch, Leon Stok: Regularity Driven Logic Synthesis. ICCAD 2000: 439-446 | |
| 12 | Frederik Beeftink, Prabhakar Kudva, David S. Kung, Ruchir Puri, Leon Stok: Combinatorial cell design for CMOS libraries. Integration 29(1): 67-93 (2000) | |
| 1999 | ||
| 11 | Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer: Wavefront Technology Mapping. DATE 1999: 531- | |
| 1998 | ||
| 10 | Frederik Beeftink, Prabhakar Kudva, David S. Kung, Leon Stok: Gate-size selection for standard cell libraries. ICCAD 1998: 545-550 | |
| 9 | Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok: Don't cares in synthesis: theoretical pitfalls and practical solutions. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 285-304 (1998) | |
| 1997 | ||
| 8 | Anirudh Devgan, Leon Stok, Sandip Kundu: Timing analysis and optimization: from devices to systems (tutorial). ICCAD 1997 | |
| 1996 | ||
| 7 | Leon Stok, David S. Kung, Daniel Brand, Anthony D. Drumm, Andrew J. Sullivan, Lakshmi N. Reddy, Nathaniel Hieter, David J. Geiger, Han Hsun Chao, Peter J. Osler: BooleDozer: Logic synthesis for ASICs. IBM Journal of Research and Development 40(4): 407-430 (1996) | |
| 6 | Guy Even, Ilan Y. Spillinger, Leon Stok: Retiming revisited and reversed. IEEE Trans. on CAD of Integrated Circuits and Systems 15(3): 348-357 (1996) | |
| 1995 | ||
| 5 | Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash: Efficient use of large don't cares in high-level and logic synthesis. ICCAD 1995: 272-278 | |
| 4 | Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok: Be careful with don't cares. ICCAD 1995: 83-86 | |
| 3 | Reinaldo A. Bergamaschi, Richard A. O'Connor, Leon Stok, Michael Z. Moricz, Shiv Prakash, Andreas Kuehlmann, D. Sreenivasa Rao: High-level synthesis in an industrial environment. IBM Journal of Research and Development 39(1-2): 131-148 (1995) | |
| 1992 | ||
| 2 | Leon Stok: False loops through resource sharing. ICCAD 1992: 345-348 | |
| 1991 | ||
| 1 | H. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon Stok: Flexible Block-Multiplier Generation. ICCAD 1991: 106-109 | |