A. Stoll

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1992

2 A. Stoll, Peter Duzy: High-Level Synthesis from VHDL with Exact Timing Constraints. DAC 1992: 188-193

1 J. Biesenack, Norbert Wehn, A. Stoll, Michael Payer: Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits 1992: 263-274

	1992
2		A. Stoll, Peter Duzy: High-Level Synthesis from VHDL with Exact Timing Constraints. DAC 1992: 188-193
1		J. Biesenack, Norbert Wehn, A. Stoll, Michael Payer: Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits 1992: 263-274

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