Chauchin Su

	2008
43		Chih-Hu Wang, Bor-Sen Chen, Bore-Kuen Lee, Tsu-Tian Lee, C.-N. J. Liu, Chauchin Su: Long-Range Prediction for Real-Time MPEG Video Traffic: An Hinfty Filter Approach. IEEE Trans. Circuits Syst. Video Techn. 18(12): 1771-1775 (2008)
	2007
42		Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1625-1636 (2007)
41		Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electronic Testing 23(4): 341-355 (2007)
	2006
40		Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen: IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC 2006: 366-371
39		Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen: IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2513-2525 (2006)
38		Wenliang Tseng, Chien-Nan Jimmy Liu, Chauchin Su: Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. IEICE Transactions 89-C(11): 1713-1718 (2006)
	2005
37		Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Oscillation ring based interconnect test scheme for SOC. ASP-DAC 2005: 184-187
36		Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen: Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium 2005: 360-365
35		Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen: Multilevel full-chip routing with testability and yield enhancement. SLIP 2005: 29-36
	2004
34		Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium 2004: 145-150
	2003
33		Chauchin Su, Chih-Hu Wang, Wei-Juo Wang, I. S. Tseng: 1149.4 Based On-Line Quiescent State Monitoring Technique. VTS 2003: 197-202
	2002
32		Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen: Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. J. Electronic Testing 18(1): 89-97 (2002)
	2001
31		Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee: A computer aided engineering system for memory BIST. ASP-DAC 2001: 492-495
30		Chauchin Su, Wenliang Tseng: Configuration free SoC interconnect BIST methodology. ITC 2001: 1033-1038
29		Yue-Tsang Chen, Chauchin Su: Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. VTS 2001: 260-265
28		Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou: Intrinsic response for analog module testing using an analog testability bus. ACM Trans. Design Autom. Electr. Syst. 6(2): 226-243 (2001)
27		Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Fault Diagnosis for Linear Analog Circuits. J. Electronic Testing 17(6): 483-494 (2001)
	2000
26		Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Fault diagnosis for linear analog circuits. Asian Test Symposium 2000: 25-30
25		Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen: Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium 2000: 338-343
24		Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su: A methodology for fault model development for hierarchical linear systems. Asian Test Symposium 2000: 90-95
23		Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee: All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. DATE 2000: 527-
22		Chauchin Su, Yue-Tsang Chen: Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. VTS 2000: 403-410
21		Chauchin Su, Yue-Tsang Chen: Intrinsic response extraction for the removal of the parasiticeffects in analog test buses. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 437-445 (2000)
20		Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su: A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. 16(5): 751-766 (2000)
19		Chauchin Su, Yue-Tsang Chen, Shenshung Chiang: Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis. J. Inf. Sci. Eng. 16(5): 767-781 (2000)
	1999
18		Chauchin Su, Yue-Tsang Chen, Chung-Len Lee: Analog Metrology and Stimulus Selection in a Noisy Environment. Asian Test Symposium 1999: 233-238
17		Chauchin Su, Shyh-Jye Jou: Decentralized BIST Methodology for System Level Interconnects. J. Electronic Testing 15(3): 255-265 (1999)
	1998
16		Chauchin Su, Yue-Tsung Chen: Comprehensive Interconnect BIST Methodology for Virtual Socket Interface. Asian Test Symposium 1998: 259-
15		Chauchin Su: A linear optimal test generation algorithm for interconnect testing. ICCAD 1998: 290-295
14		Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen: Boundary scan BIST methodology for reconfigurable systems. ITC 1998: 774-783
	1997
13		Chauchin Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen: Analog signal metrology for mixed signal ICs. Asian Test Symposium 1997: 194-
12		Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou: Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. ITC 1997: 499-508
	1996
11		Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting: Syndrome Simulation And Syndrome Test For Unscanned Interconnects. Asian Test Symposium 1996: 62-67
10		Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting: Metrology for analog module testing using analog testability bus. ICCAD 1996: 594-599
	1995
9		Chauchin Su, Shenshung Chiang, Shyh-Jye Jou: Impulse response fault model and fault extraction for functional level analog circuit diagnosis. ICCAD 1995: 631-636
8		Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su: Circuits Design Optimization Using Symbolic Approach. ISCAS 1995: 1396-1399
7		Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su: A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. ISCAS 1995: 574-577
	1994
6		Chauchin Su: Random Testing of Interconnects in A Boundary Scan Environment. EDAC-ETC-EUROASIC 1994: 226-231
5		Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang: Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. ISCAS 1994: 21-24
4		Chauchin Su, Kychin Hwang, Shyh-Jye Jou: An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment. ITC 1994: 670-676
	1993
3		Chiyuan Chang, Chauchin Su: A Universal BIST Methodology for Interconnects. ISCAS 1993: 1615-1618
2		Chauchin Su, Jyrghong Wang: ECCSyn: a Synthesis Tool for ECC Circuits. ISCAS 1993: 1706-1709
1		Chauchin Su, Kychin Hwang: A Serial-Scan Test-Vector-Compression Methodology. ITC 1993: 981-988

Coauthor Index

1	Chiyuan Chang	[3]
2	Yao-Wen Chang	[35] [39] [40] [42]
3	Yeong-Jar Chang	[20]
4	Bor-Sen Chen	[43]
5	Gen-Nan Chen	[23]
6	Jwu E. Chen	[20] [24] [25] [26] [27] [34] [35] [36] [37] [39] [40] [41] [42]
7	Jwu-E Chen	[32]
8	Yue-Tsang Chen	[10] [12] [13] [14] [18] [19] [21] [22] [23] [28] [29]
9	Yue-Tsung Chen	[16]
10	Yi-Ren Cheng	[13]
11	Shenshung Chiang	[9] [19]
12	Shih-Ching Hsiao	[31]
13	Wen-Hsing Hsieh	[7]
14	Mu-Jeng Huang	[23]
15	Yin-Chao Huang	[24]
16	Kychin Hwang	[1] [4]
17	Shyh-Shen Hwang	[11]
18	Shung-Won Jeng	[14]
19	Tagin Jiang	[36]
20	Shyh-Jye Jou	[4] [5] [7] [8] [9] [10] [11] [12] [17] [28]
21	Bore-Kuen Lee	[43]
22	Chung-Len Lee	[18] [20] [23] [24] [25] [26] [27] [31] [32] [34] [35] [36] [37] [39] [40] [41] [42]
23	Tsu-Tian Lee	[43]
24	Katherine Shu-Min Li	[34] [35] [36] [37] [39] [40] [41] [42]
25	Jun-Weir Lin	[24] [26] [27]
26	C.-N. J. Liu	[43]
27	Chien-Nan Jimmy Liu	[38]
28	Kou-Fong Liu	[8]
29	Chih-Wen Lu	[25] [32]
30	Mei-Fang Perng	[5]
31	Shing Tenchen	[13]
32	Yuan-Tzu Ting	[10] [11]
33	I. S. Tseng	[33]
34	Wenliang Tseng	[30] [38]
35	C. K. Wang	[5]
36	Chih-Hu Wang	[33] [43]
37	Jyrghong Wang	[2]
38	Wei-Juo Wang	[33]
39	Hau-Zen Zhau	[31]

Colors in the list of coauthors