Makoto Sugihara

	2009
15		Makoto Sugihara: Reliability Inherent in Heterogeneous Multiprocessor Systems and Task Scheduling for Ameliorating Their Reliability. IEICE Transactions 92-A(4): 1121-1128 (2009)
	2008
14		Makoto Sugihara: SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems. ISQED 2008: 757-762
13		Makoto Sugihara, Yusuke Matsunaga, Kazuaki Murakami: Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. IEICE Transactions 91-A(12): 3451-3460 (2008)
12		Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. IEICE Transactions 91-C(4): 410-417 (2008)
	2007
11		Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Task scheduling for reliable cache architectures of multiprocessor systems. DATE 2007: 1490-1495
10		Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. IEICE Transactions 90-C(10): 1983-1991 (2007)
9		Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki Murakami: Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. IEICE Transactions 90-C(5): 1012-1020 (2007)
	2006
8		Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura: A character size optimization technique for throughput enhancement of character projection lithography. ISCAS 2006
7		Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto: A Simulation-Based Soft Error Estimation Methodology for Computer Systems. ISQED 2006: 196-203
6		Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura: Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Transactions 89-C(3): 377-383 (2006)
	2004
5		Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga: Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. ISVLSI 2004: 179-186
	2002
4		Makoto Sugihara, Hiroto Yasuura: Optimization of Test Accesses with a Combined BIST and External Test Scheme. VLSI Design 2002: 683-688
	2000
3		Makoto Sugihara, Hiroto Yasuura, Hiroshi Date: Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. DATE 2000: 134-140
2		Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara: Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. PDPTA 2000
	1998
1		Makoto Sugihara, Hiroshi Date, Hiroto Yasuura: A novel test methodology for core-based system LSIs and a testing time minimization problem. ITC 1998: 465-

Coauthor Index

1	Krishnendu Chakrabarty	[2]
2	Hiroshi Date	[1] [2] [3]
3	Tetsuya Hasebe	[6] [8]
4	Koji Hashimoto	[7]
5	Hiroaki Hayashi	[6] [8]
6	Ryoichi Inanami	[6] [8]
7	Tohru Ishihara	[7] [10] [11] [12]
8	Vikram Iyengar	[2]
9	Yukihiro Kawano	[6] [8]
10	Katsumi Kishimoto	[6] [8]
11	Yusuke Matsunaga	[5] [6] [8] [9] [13]
12	Kazuaki Murakami	[5] [6] [8] [9] [10] [11] [12] [13]
13	Masanori Muroyama	[7]
14	Kenta Nakamura	[6] [8] [9]
15	Katsuya Okumura	[6] [8]
16	Taiga Takata	[6] [8]
17	Hiroto Yasuura	[1] [3] [4]