Hyuk-Jun Sung

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1999

1 Hyuk-Jun Sung, Kwang Sub Yoon: A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. ISCAS (2) 1999: 553-556

	1999
1		Hyuk-Jun Sung, Kwang Sub Yoon: A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. ISCAS (2) 1999: 553-556

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