 | 2008 |
|---|
| 15 |       | Hsi-Chin Hsin,
Tze-Yun Sung:
Adaptive Selection and Rearrangement of Wavelet Packets for Quad-Tree Image Coding.
IEICE Transactions 91-A(9): 2655-2662 (2008) |
| 2007 |
|---|
| 14 |  | Hsi-Chin Hsin,
Jenn-Jier Lien,
Tze-Yun Sung:
A Hybrid SPIHT-EBC Image Coder.
IMECS 2007: 1854-1857 |
| 13 | | Tze-Yun Sung,
Hsi-Chin Hsin:
A Hybrid Image Coder Based on SPIHT Algorithm with Embedded Block Coding.
IEICE Transactions 90-A(12): 2979-2984 (2007) |
| 12 | | Tze-Yun Sung,
Hsi-Chin Hsin:
Fixed-Point Error Analysis of CORDIC Arithmetic for Special-Purpose Signal Processors.
IEICE Transactions 90-A(9): 2006-2013 (2007) |
| 11 | | Tze-Yun Sung,
Hsi-Chin Hsin:
An Efficient Rearrangement of Wavelet Packet Coefficients for Embedded Image Coding Based on SPIHT Algorithm.
IEICE Transactions 90-A(9): 2014-2020 (2007) |
| 2006 |
|---|
| 10 | | Tze-Yun Sung:
A High-Efficient Image Scalar Algorithm for LCD Signal Processor.
JCIS 2006 |
| 9 | | Tze-Yun Sung:
A High-Efficient Line-Based Architecture for 2-D Lifting-Based DWT Using 9/7 Wavelet Filters.
JCIS 2006 |
| 8 | | Tze-Yun Sung:
A High-Efficient and Cost-Effective LCD Signal Processor.
JCIS 2006 |
| 7 | | Tze-Yun Sung:
An Efficient CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphics Rendering.
JCIS 2006 |
| 6 | | Tze-Yun Sung:
High-Efficient Architectures for 2-D Lifting-Based Forward and Inverse Discrete Wavelet Transform.
JCIS 2006 |
| 5 | | Tze-Yun Sung:
High-Speed and Low-Power Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-ta.
JCIS 2006 |
| 4 | | Tze-Yun Sung,
Yaw-Shih Shieh,
Chun-Wang Yu,
Hsi-Chin Hsin:
Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters.
PDCAT 2006: 185-190 |
| 3 | | Tze-Yun Sung,
Yaw-Shih Shieh,
Chun-Wang Yu,
Hsi-Chin Hsin:
High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation.
PDCAT 2006: 191-196 |
| 2 | | Tze-Yun Sung,
Yaw-Shih Shieh,
Chun-Wang Yu,
Hsi-Chin Hsin:
A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering.
PDCAT 2006: 44-49 |
| 1 | | Tze-Yun Sung,
Mao-Jen Sun,
Yaw-Shih Shieh,
Hsi-Chin Hsin:
Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation.
PSIVT 2006: 802-811 |
