Sureshchander

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1978

2 Sureshchander: Comments on ``Delayed Universal Logic Modules and Sequential Machine Synthesis''. IEEE Trans. Computers 27(2): 191 (1978)

1975

1 Sureshchander: Minimization of Switching Functions - A Fast Technique. IEEE Trans. Computers 24(7): 753-756 (1975)

	1978
2		Sureshchander: Comments on ``Delayed Universal Logic Modules and Sequential Machine Synthesis''. IEEE Trans. Computers 27(2): 191 (1978)
	1975
1		Sureshchander: Minimization of Switching Functions - A Fast Technique. IEEE Trans. Computers 24(7): 753-756 (1975)