 | 2007 |
|---|
| 8 |       | Vasutan Tunbunheng,
Masayasu Suzuki,
Hideharu Amano:
Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices.
IEICE Transactions 90-D(2): 473-481 (2007) |
| 2006 |
|---|
| 7 | | Masayasu Suzuki,
Yohei Hasegawa,
Vu Manh Tuan,
Shohei Abe,
Hideharu Amano:
A cost-effective context memory structure for dynamically reconfigurable processors.
IPDPS 2006 |
| 2005 |
|---|
| 6 |  | Katsuaki Deguchi,
Shohei Abe,
Masayasu Suzuki,
Kenichiro Anjo,
Toru Awashima,
Hideharu Amano:
Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor.
ARCS Workshops 2005: 12-18 |
| 5 | | Hideharu Amano,
Shohei Abe,
Yohei Hasegawa,
Katsuaki Deguchi,
Masayasu Suzuki:
Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor.
FCCM 2005: 315-316 |
| 4 | | Yohei Hasegawa,
Shohei Abe,
Katsuaki Deguchi,
Masayasu Suzuki,
Hideharu Amano:
Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation.
FPGA 2005: 265 |
| 3 | | Vasutan Tunbunheng,
Masayasu Suzuki,
Hideharu Amano:
RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices.
FPT 2005: 129-136 |
| 2004 |
|---|
| 2 | | Noriaki Suzuki,
Shunsuke Kurotaki,
Masayasu Suzuki,
Naoto Kaneko,
Yutaka Yamada,
Katsuaki Deguchi,
Yohei Hasegawa,
Hideharu Amano,
Kenichiro Anjo,
Masato Motomura,
Kazutoshi Wakabayashi,
Takeo Toi,
Toru Awashima:
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
FCCM 2004: 328-329 |
| 1 | | Hideharu Amano,
Takeshi Inuo,
Hirokazu Kami,
Taro Fujii,
Masayasu Suzuki:
Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases.
FPL 2004: 464-473 |
