 | 2008 |
|---|
| 11 |       | Kazuhiro Nakamura,
Masatoshi Yamamoto,
Kazuyoshi Takagi,
Naofumi Takagi:
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems.
ISCAS 2008: 1688-1691 |
| 10 | | Koji Obata,
Kazuyoshi Takagi,
Naofumi Takagi:
A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits.
IEICE Transactions 91-A(12): 3772-3782 (2008) |
| 2007 |
|---|
| 9 | | Katsuki Kobayashi,
Naofumi Takagi,
Kazuyoshi Takagi:
An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2).
IEEE Symposium on Computer Arithmetic 2007: 105-112 |
| 8 | | Koji Obata,
Kazuyoshi Takagi,
Naofumi Takagi:
Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams.
IEICE Transactions 90-A(1): 257-266 (2007) |
| 7 | | Koji Obata,
Kazuyoshi Takagi,
Naofumi Takagi:
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits.
IEICE Transactions 90-C(12): 2278-2284 (2007) |
| 2006 |
|---|
| 6 | | Shigeru Yamashita,
Katsunori Tanaka,
Hideyuki Takada,
Koji Obata,
Kazuyoshi Takagi:
A transduction-based framework to synthesize RSFQ circuits.
ASP-DAC 2006: 266-272 |
| 5 | | Naofumi Takagi,
Shunsuke Kadowaki,
Kazuyoshi Takagi:
A Hardware Algorithm for Integer Division Using the SD2 Representation.
IEICE Transactions 89-A(10): 2874-2881 (2006) |
| 2005 |
|---|
| 4 | | Naofumi Takagi,
Shunsuke Kadowaki,
Kazuyoshi Takagi:
A Hardware Algorithm for Integer Division.
IEEE Symposium on Computer Arithmetic 2005: 140-146 |
| 2001 |
|---|
| 3 | | Naofumi Takagi,
Jun-ichi Yoshiki,
Kazuyoshi Takagi:
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis.
IEEE Trans. Computers 50(5): 394-398 (2001) |
| 2000 |
|---|
| 2 | | Shinji Kimura,
Hiroyuki Kida,
Kazuyoshi Takagi,
Tatsumori Abematsu,
Katsumasa Watanabe:
An application specific Java processor with reconfigurabilities.
ASP-DAC 2000: 25-26 |
| 1998 |
|---|
| 1 | | Kazuhiro Nakamura,
Kazuyoshi Takagi,
Shinji Kimura,
Katsumasa Watanabe:
Waiting false path analysis of sequential logic circuits for performance optimization.
ICCAD 1998: 392-395 |
