| 2009 | ||
|---|---|---|
| 56 | Corneliu Rusu, Lacrimioara Grama, Jarmo Takala: SPICE Simulation of Analog Filters: A Method for Designing Digital Filters. EUROCAST 2009: 534-539 | |
| 55 | Ismo Hänninen, Jarmo Takala: Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata. SAMOS 2009: 118-127 | |
| 54 | Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala: Programmable and Scalable Architecture for Graphics Processing Units. SAMOS 2009: 2-11 | |
| 53 | Jari Heikkinen, Jarmo Takala, Henk Corporaal: Dictionary-based program compression on customizable processor architectures. Microprocessors and Microsystems - Embedded Hardware Design 33(2): 139-153 (2009) | |
| 52 | Teemu Pitkänen, Jarno K. Tanskanen, Risto Mäkinen, Jarmo Takala: Parallel Memory Architecture for Application-Specific Instruction-Set Processors. Signal Processing Systems 57(1): 21-32 (2009) | |
| 2008 | ||
| 51 | Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala, Heikki Kultala, Mikael Lepistö: Reducing Context Switch Overhead with Compiler-Assisted Threading. EUC (2) 2008: 461-466 | |
| 50 | Jin Li, Moncef Gabbouj, Jarmo Takala, Hexin Chen: Laplacian modeling of DCT coefficients for real-time encoding. ICME 2008: 797-800 | |
| 49 | Ismo Hänninen, Jarmo Takala: Reliability of n-Bit Nanotechnology Adder. ISVLSI 2008: 34-39 | |
| 48 | Daniel Iancu, Mayan Moudgill, John Glossner, Jarmo Takala: Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set. SAMOS 2008: 126-135 | |
| 47 | Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala: Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic. SAMOS 2008: 23-32 | |
| 46 | Ismo Hänninen, Jarmo Takala: Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology. SAMOS 2008: 43-52 | |
| 45 | Perttu Salmela, Harri Sorokin, Jarmo Takala: Low-complexity polynomials modulo integer with linearly incremented variable. SiPS 2008: 251-256 | |
| 44 | Shuvra S. Bhattacharyya, Jarmo Takala, Georgi Gaydadjiev: Introduction to the Special Issue on Embedded Computing Systems for DSP. Signal Processing Systems 50(2): 97-98 (2008) | |
| 2007 | ||
| 43 | Ismo Hänninen, Jarmo Takala: Robust Adders Based on Quantum-Dot Cellular Automata. ASAP 2007: 391-396 | |
| 42 | Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala: Resource Conflict Detection in Simulation of Function Unit Pipelines. SAMOS 2007: 233-240 | |
| 41 | Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala: Parallel Memory Architecture for TTA Processor. SAMOS 2007: 273-282 | |
| 40 | Teemu Pitkänen, Tero Partanen, Jarmo Takala: Low-Power Twiddle Factor Unit for FFT Computation. SAMOS 2007: 65-74 | |
| 39 | Perttu Salmela, Chung-Ching Shen, Shuvra S. Bhattacharyya, Jarmo Takala: Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations. SiPS 2007: 475-480 | |
| 38 | Perttu Salmela, Juho Antikainen, Olli Silvén, Jarmo Takala: Memory-Based List Updating for List Sphere Decoders. SiPS 2007: 633-638 | |
| 37 | Jari Heikkinen, Jarmo Takala: Effects of program compression. Journal of Systems Architecture 53(10): 679-688 (2007) | |
| 36 | Jarmo Takala, Timo D. Hämäläinen, Andy D. Pimentel, Stamatis Vassiliadis: Editorial. Journal of Systems Architecture 53(8): 465 (2007) | |
| 35 | Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala: Stride Permutation Networks for Array Processors. VLSI Signal Processing 49(1): 51-71 (2007) | |
| 2006 | ||
| 34 | Georgi Gaydadjiev, C. John Glossner, Jarmo Takala, Stamatis Vassiliadis: Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006 IEEE 2006 | |
| 33 | Tuomas Järvinen, Perttu Salmela, Konsta Punkka, Jarmo Takala: Evaluation of stride permutation networks. ISCAS 2006 | |
| 32 | Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala: Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform. SAMOS 2006: 227-236 | |
| 31 | Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala: Software Pipelining Support for Transport Triggered Architecture Processors. SAMOS 2006: 237-247 | |
| 30 | Jari Heikkinen, Jarmo Takala: Effects of Program Compression. SAMOS 2006: 259-268 | |
| 29 | Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala: Software Implementation of WiMAX on the Sandbridge SandBlaster Platform. SAMOS 2006: 435-446 | |
| 28 | Jari Nikara, Jarmo Takala, Jaakko Astola: Discrete cosine and sine transforms - regular algorithms and pipeline architectures. Signal Processing 86(2): 230-249 (2006) | |
| 27 | Jarmo Takala, Konsta Punkka: Scalable FFT Processors and Pipelined Butterfly Units. VLSI Signal Processing 43(2-3): 113-123 (2006) | |
| 2005 | ||
| 26 | Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, Stamatis Vassiliadis: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings Springer 2005 | |
| 25 | Adrian Burian, Perttu Salmela, Jarmo Takala: Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture. ASAP 2005: 107-112 | |
| 24 | Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala: 256-State Rate 1/2 Viterbi Decoder on TTA Processor. ASAP 2005: 370-378 | |
| 23 | Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal: Dictionary-based program compression on transport triggered architectures. ISCAS (2) 2005: 1122-1125 | |
| 22 | Teemu Pitkänen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala: Hardware Cost Estimation for Application-Specific Processor Design. SAMOS 2005: 212-221 | |
| 21 | Tuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala: Systematic approach for path metric access in Viterbi decoders. IEEE Transactions on Communications 53(5): 755-759 (2005) | |
| 2004 | ||
| 20 | Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala: Stride Permutation Networks for Array Processors. ASAP 2004: 376-386 | |
| 19 | Adrian Burian, Jarmo Takala: VLSI-efficient implementation of full adder-based median filter. ISCAS (2) 2004: 817-820 | |
| 18 | Mikko Ylinen, Adrian Burian, Jarmo Takala: Direct versus iterative methods for fixed-point implementation of matrix inversion. ISCAS (3) 2004: 225-228 | |
| 17 | Riku Uusikartano, Jarmo Takala: A low-power fractional decimator architecture for an IF-sampling dual-mode receiver. ISCAS (3) 2004: 589-592 | |
| 16 | Tuomas Järvinen, Jarmo Takala: Register-Based Permutation Networks for Stride Permutations. SAMOS 2004: 108-117 | |
| 15 | Jarmo Takala, Konsta Punkka: Scalable FFT Processors and Pipelined Butterfly Units. SAMOS 2004: 373-382 | |
| 14 | Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha: Multiple-symbol parallel decoding for variable length codes. IEEE Trans. VLSI Syst. 12(7): 676-685 (2004) | |
| 2003 | ||
| 13 | Adrian Burian, Jarmo Takala, Marina Dana Topa: Parallel iterations for recursive median filter. ISCAS (4) 2003: 488-491 | |
| 12 | Jarmo Takala, Tuomas Järvinen, Harri Sorokin: Conflict-free parallel memory access scheme for FFT processors. ISCAS (4) 2003: 524-527 | |
| 11 | Adrian Burian, Jarmo Takala: A recurrent neural network for 1-D phase retrieval. ISCAS (5) 2003: 729-732 | |
| 10 | Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal: Evaluating Template-Based Instruction Compression on Transport Triggered Architectures. IWSOC 2003: 192-195 | |
| 9 | Jussi Nykänen, Harri Klapuri, Jarmo Takala: Mapping Action Systems to Hardware Descriptions. PDPTA 2003: 1407-1412 | |
| 8 | Tuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala: In-Place Storage of Path Metrics in Viterbi Decoders. VLSI-SOC 2003: 295-300 | |
| 7 | Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha: FPGA-Based Variable Length Decoders. VLSI-SOC 2003: 437-441 | |
| 2002 | ||
| 6 | Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Mihai Sima, Petri Liuha: Parallel Multiple-Symbol Variable-Length Decoding. ICCD 2002: 126-131 | |
| 5 | Jarmo Takala, Tuomas Järvinen, Jari Nikara: Register-based reordering networks for matrix transpose. ISCAS (4) 2002: 874-877 | |
| 2001 | ||
| 4 | Tuomas Järvinen, Jarmo Takala, David Akopian, Jukka Saarinen: Register-based multi-port perfect shuffle networks. ISCAS (4) 2001: 306-309 | |
| 3 | Jari Nikara, Jarmo Takala, David Akopian, Jukka Saarinen: Pipeline architecture for DCT/IDCT. ISCAS (4) 2001: 902-905 | |
| 1999 | ||
| 2 | Jarmo Takala, Jouko O. Viitanen: Distance Transform Algorithm for Bit-Serial SIMD Architectures. Computer Vision and Image Understanding 74(2): 150-161 (1999) | |
| 1994 | ||
| 1 | Jouko O. Viitanen, Jarmo Takala: SIMD Parallel Calculation of Distance Transformations. ICIP (3) 1994: 645-649 | |