Yasuhiro Takashima

	2008
14		Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi: ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. ISCAS 2008: 1800-1803
13		Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi: Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. IEICE Transactions 91-A(12): 3539-3547 (2008)
12		Yuko Hashizume, Yasuhiro Takashima, Yuichi Nakamura: Post-Silicon Clock-Timing Tuning Based on Statistical Estimation. IEICE Transactions 91-A(9): 2322-2327 (2008)
	2007
11		Tan Yan, Shuting Li, Yasuhiro Takashima, H. Murata: A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks. ASP-DAC 2007: 268-273
10		Kunihiko Yanagibashi, Yasuhiro Takashima, Yuichi Nakamura: A Relocation Method for Circuit Modifications. IEICE Transactions 90-A(12): 2743-2751 (2007)
9		Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani: A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. IEICE Transactions 90-A(5): 924-931 (2007)
	2006
8		Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani: How does partitioning matter for 3D floorplanning? ACM Great Lakes Symposium on VLSI 2006: 73-78
7		Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: The Oct-Touched Tile: A New Architecture for Shape-Based Routing. IEICE Transactions 89-A(2): 448-455 (2006)
	2005
6		Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: The oct-touched tile: a new architecture for shape-based routing. ACM Great Lakes Symposium on VLSI 2005: 126-129
	2004
5		Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: A device-level placement with multi-directional convex clustering. ACM Great Lakes Symposium on VLSI 2004: 196-201
4		Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani: Abstraction and optimization of consistent floorplanning with pillar block constraints. ASP-DAC 2004: 19-24
3		Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: Multi-level placement with circuit schema based clustering in analog IC layouts. ASP-DAC 2004: 406-411
2		Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake: A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. ISCAS (4) 2004: 489-492
	2000
1		Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC 2000: 87-92

Coauthor Index

1	Qing Dong	[8]
2	Ning Fu	[4] [6] [7]
3	Yuko Hashizume	[12]
4	Masato Inagi	[9] [13] [14]
5	Yoji Kajitani	[1] [3] [4] [5] [6] [7] [8] [9]
6	Keiji Kida	[2]
7	Yukiko Kubo	[1]
8	Shuting Li	[11]
9	H. Murata	[11]
10	Yuichi Nakamura (Yuhichi Nakamura)	[9] [10] [12] [13] [14]
11	Shigetoshi Nakatake	[1] [2] [3] [4] [5] [6] [7]
12	Takashi Nojima	[3] [5]
13	Atsushi Takahashi	[13] [14]
14	Tan Yan	[8] [11]
15	Kunihiko Yanagibashi	[10]
16	Xiaoke Zhu	[2] [3]
17	Changwen Zhuang	[2]