Koichi Tanno

	2008
17		Hisashi Tanaka, Koichi Tanno, Hiroki Tamura, Kenji Murao: Design of CMOS OTAs for Low-Voltage and Low-Power Application. IEICE Transactions 91-A(11): 3385-3388 (2008)
16		Hiroki Tamura, Koichi Tanno: Midpoint-Validation Method for Support Vector Machine Classification. IEICE Transactions 91-D(7): 2095-2098 (2008)
	2006
15		Muneo Kushima, Motoi Inaba, Koichi Tanno: Linear and Compact Floating Node Voltage-Controlled Variable Resistor Circuit. IEICE Transactions 89-A(2): 459-460 (2006)
	2005
14		Koichi Tanno, Kiminobu Sato, Hisashi Tanaka, Okihiko Ishizuka: Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit. IEICE Transactions 88-A(10): 2696-2698 (2005)
13		Koichi Tanno, Kenya Kondo, Okihiko Ishizuka, Takako Toyama: Combiner-Based MOS OTAs. IEICE Transactions 88-A(6): 1622-1625 (2005)
	2002
12		Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. ISMVL 2002: 282-
	2001
11		Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators. ISMVL 2001: 27-
10		Koichi Tashima, Zheng Tang, Okihiko Ishizuka, Koichi Tanno: An immune network with interactions between B cells for pattern recognition. Systems and Computers in Japan 32(10): 31-41 (2001)
	2000
9		Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. ISMVL 2000: 15-20
8		Makoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka: Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions. ISMVL 2000: 27-32
	1999
7		Jing Shen, Koichi Tanno, Okihiko Ishizuka: Down Literal Circuit with Neuron-MOS Transistors and Its Applications. ISMVL 1999: 180-185
	1998
6		Jing Shen, Koichi Tanno, Okihiko Ishizuka, Zheng Tang: Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits. ISMVL 1998: 128-133
	1997
5		Okihiko Ishizuka, Akihiro Ohta, Koichi Tanno, Zheng Tang, Dwi Handoko: VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products. ISMVL 1997: 169-174
4		Zheng Tang, T. Yamaguchi, Koichi Tashima, Okihiko Ishizuka, Koichi Tanno: Multiple-Valued Immune Network Model and Its Simulations. ISMVL 1997: 233-
	1995
3		Koichi Tanno, Akio Koyama, T. Taketa, Shoichi Noguchi: Buffer insertion/self-token (BIST) protocol for multimedia LANs. ICNP 1995: 350-355
2		Zheng Tang, Yuichi Shirata, Okihiko Ishizuka, Koichi Tanno: A Self-Calibrating A/D Converter Using T-Model Neural Network. ISCAS 1995: 533-536
1		Zheng Tang, Okihiko Ishizuka, Koichi Tanno: Learning Multiple-Valued Logic Networks Based on Back Propagation. ISMVL 1995: 270-275

Coauthor Index

1	Dwi Handoko	[5]
2	Motoi Inaba	[9] [11] [12] [15]
3	Okihiko Ishizuka	[1] [2] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
4	Kenya Kondo	[13]
5	Akio Koyama	[3]
6	Muneo Kushima	[15]
7	Kenji Murao	[17]
8	Shoichi Noguchi	[3]
9	Akihiro Ohta	[5]
10	Kiminobu Sato	[14]
11	Jing Shen	[6] [7] [8] [9]
12	Yuichi Shirata	[2]
13	Makoto Syuto	[8]
14	T. Taketa	[3]
15	Hiroki Tamura	[16] [17]
16	Hisashi Tanaka	[14] [17]
17	Zheng Tang	[1] [2] [4] [5] [6] [10]
18	Koichi Tashima	[4] [10]
19	Takako Toyama	[13]
20	T. Yamaguchi	[4]

Colors in the list of coauthors