Mohammad H. Tehranipour

	2005
14		Mehrdad Nourani, Mohammad H. Tehranipour: RL-huffman encoding for test compression and power reduction in scan applications. ACM Trans. Design Autom. Electr. Syst. 10(1): 91-115 (2005)
	2004
13		Mohammad H. Tehranipour, Mehrdad Nourani, Krishnendu Chakrabarty: Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression. DATE 2004: 1284-1289
12		Mohammad H. Tehranipour, Mehrdad Nourani, Karim Arabi, Ali Afzali-Kusha: Mixed RL-Huffman encoding for power reduction and data compression in scan test. ISCAS (2) 2004: 681-684
11		Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani: Low power pattern generation for BIST architecture. ISCAS (2) 2004: 689-692
10		Nisar Ahmed, Mohammad H. Tehranipour, Dian Zhou, Mehrdad Nourani: Frequency driven repeater insertion for deep submicron. ISCAS (5) 2004: 181-184
9		Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani: Testing SoC interconnects for signal integrity using extended JTAG architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 800-811 (2004)
8		Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin: A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. J. Electronic Testing 20(2): 155-168 (2004)
	2003
7		Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani: Extending JTAG for Testing Signal Integrity in SoCs. DATE 2003: 10218-10223
6		Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani: Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity. ICCD 2003: 554-
5		G. R. Chaji, R. M. Pourrad, Seid Mehdi Fakhraie, Mohammad H. Tehranipour: eUTDSP: a design study of a new VLIW-based DSP architecture. ISCAS (4) 2003: 137-140
4		Mohammad H. Tehranipour, Mehrdad Nourani, Seid Mehdi Fakhraie, Ali Afzali-Kusha: Systematic test program generation for SoC testing using embedded processor. ISCAS (5) 2003: 541-544
3		Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani: Testing SoC Interconnects for Signal Integrity Using Boundary Scan. VTS 2003: 158-172
	2002
2		Mohammad H. Tehranipour, Mehrdad Nourani: Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor. ITC 2002: 1093-1102
	2001
1		Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie: An efficient BIST method for testing of embedded SRAMs. ISCAS (5) 2001: 73-76

Coauthor Index

1	Ali Afzali-Kusha	[4] [12]
2	Nisar Ahmed	[3] [6] [7] [9] [10] [11]
3	Karim Arabi	[12]
4	G. R. Chaji	[5]
5	Krishnendu Chakrabarty	[13]
6	Sied Mehdi Fakhraie (Seid Mehdi Fakhraie)	[1] [4] [5] [8]
7	M. R. Movahedin	[8]
8	Zainalabedin Navabi	[1] [8]
9	Mehrdad Nourani	[2] [3] [4] [6] [7] [9] [10] [11] [12] [13] [14]
10	R. M. Pourrad	[5]
11	Dian Zhou	[10]