 | 2002 |
|---|
| 10 |       | Jinan Lou,
Shashidhar Thakur,
Shankar Krishnamoorthy,
Henry S. Sheng:
Estimating routing congestion using probabilistic analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 32-41 (2002) |
| 1997 |
|---|
| 9 | | Shashidhar Thakur,
Yao-Wen Chang,
Martin D. F. Wong,
S. Muthukrishnan:
Algorithms for an FPGA switch module routing problem with application to global routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 32-46 (1997) |
| 1996 |
|---|
| 8 | | Shashidhar Thakur,
D. F. Wong,
Shankar Krishnamoorthy:
Delay Minimal Decomposition of Multiplexers in Technology Mapping.
DAC 1996: 254-257 |
| 7 | | Shashidhar Thakur,
D. F. Wong:
Universal Logic Modules for Series-Parallel Functions.
FPGA 1996: 31-37 |
| 6 | | Shashidhar Thakur,
D. F. Wong:
Series-parallel functions and FPGA logic module design.
ACM Trans. Design Autom. Electr. Syst. 1(1): 102-122 (1996) |
| 1995 |
|---|
| 5 | | Shashidhar Thakur,
D. F. Wong:
On Designing ULM-based FPGA Logic Modules.
FPGA 1995: 3-9 |
| 4 | | Shashidhar Thakur,
D. F. Wong:
Simultaneous area and delay minimum K-LUT mapping for K-exact networks.
ICCD 1995: 402-408 |
| 3 |  | Shashidhar Thakur,
Kai-Yuan Chao,
D. F. Wong:
An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing.
ISCAS 1995: 207-210 |
| 1994 |
|---|
| 2 | | Shashidhar Thakur,
D. F. Wong,
S. Muthukrishnan:
Algorithms for a switch module routing problem.
EURO-DAC 1994: 265-270 |
| 1 | | Yao-Wen Chang,
Shashidhar Thakur,
Kai Zhu,
D. F. Wong:
A new global routing algorithm for FPGAs.
ICCAD 1994: 356-361 |
