Adonios Thanailakis

Antonios Thanailakis

2007
56	EE	Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis: Designing Heterogeneous FPGAs with Multiple SBs. ARC 2007: 91-96
55	EE	Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck CoRR abs/0710.4656: (2007)
54	EE	Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis: Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. Integration 40(2): 74-93 (2007)
53	EE	Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement. Journal of Systems Architecture 53(7): 417-436 (2007)
2006
52	EE	Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. DATE 2006: 740-745
51	EE	K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis: A novel methodology for designing high-performance and low-energy FPGA routing architecture. FPGA 2006: 224
50	EE	Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. IPDPS 2006
49	EE	Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis: A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. ISCAS 2006
48	EE	Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. PATMOS 2006: 403-414
47	EE	Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. VLSI-SoC 2006: 204-209
46	EE	Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance. Computer Communications 29(13-14): 2612-2620 (2006)
45	EE	Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis: A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. IEEE Trans. VLSI Syst. 14(3): 279-291 (2006)
44	EE	Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis: Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. VLSI Signal Processing 44(1-2): 153-171 (2006)
2005
43	EE	Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, K. Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis: AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. ASP-DAC 2005: 3-4
42	EE	Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. DATE 2005: 946-947
41		K. Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis: An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. FPL 2005: 658-661
40		K. Siozios, Dimitrios Soudris, Adonios Thanailakis: A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. FPL 2005: 707-708
39		Nikolas Kroupis, Minas Dasygenis, Dimitrios Soudris, Antonios Thanailakis: A Modified Spiral Search Algorithm and its Embedded Hardware Implementation. IEC (Prague) 2005: 375-378
38	EE	K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. IPDPS 2005
37	EE	Nikolas Kroupis, Minas Dasygenis, K. Markou, Dimitrios Soudris, Adonios Thanailakis: A modified spiral search motion estimation algorithm and its embedded system implementation. ISCAS (4) 2005: 3347-3350
36	EE	Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Improving the Memory Bandwidth Utilization Using Loop Transformations. PATMOS 2005: 117-126
35	EE	Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis: Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. WWIC 2005: 354-364
34	EE	Georgios Ch. Sirakoulis, V. Raptis, Ioannis Karafyllidis, Phillipos Tsalides, Adonios Thanailakis: A fault-tolerant message passing algorithm and its hardware implementation. Advances in Engineering Software 36(3): 159-171 (2005)
33	EE	Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos: A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. IEICE Transactions 88-D(7): 1369-1380 (2005)
32	EE	Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis: A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. Journal of Circuits, Systems, and Computers 14(2): 281-296 (2005)
2004
31	EE	K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. FPL 2004: 1116-1118
30	EE	Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis: An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. IPDPS 2004
29	EE	Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis: A reusable IP FFT core for DSP applications. ISCAS (3) 2004: 621-624
28	EE	Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications. SAMOS 2004: 540-549
27	EE	Stylianos Mamagkakis, Alexandros Mpartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Antonios Thanailakis: Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. WWIC 2004: 26-37
26	EE	Ioannis Tsimperidis, Ioannis Karafyllidis, Antonios Thanailakis: Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gate. Microelectronics Journal 35(5): 471-478 (2004)
2003
25	EE	Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis: Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. FPL 2003: 1032-1035
24	EE	Dimitrios Soudris, Marios Kesoulis, C. Koukourlis, Adonios Thanailakis, Spyros Blionas: Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size. ISCAS (2) 2003: 73-76
23	EE	Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis: A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. ISCAS (5) 2003: 129-132
22	EE	Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas: Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. PATMOS 2003: 430-439
21	EE	Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis: FPGA Architecture Design and Toolset for Logic Implementation. PATMOS 2003: 607-616
20		Marios Kesoulis, Dimitrios Soudris, C. Koukourlis, Adonios Thanailakis: Designing Low Power Direct Digital Frequency Synthesizers. VLSI-SOC 2003: 105-110
19	EE	Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis: A CAD system for the construction and VLSI implementation of Cellular Automata algorithms using VHDL. Microprocessors and Microsystems 27(8): 381-396 (2003)
18	EE	Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis: Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. Real-Time Imaging 9(6): 371-386 (2003)
2002
17	EE	George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis: Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. FPL 2002: 1027-1036
16	EE	Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis: A cellular automaton methodology for the simulation of integrated circuit fabrication processes. Future Generation Comp. Syst. 18(5): 639-657 (2002)
15	EE	S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis: A fast and accurate delay dependent method for switching estimation of large combinational circuits. Journal of Systems Architecture 48(4-5): 113-124 (2002)
2001
14	EE	Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis: Power, performance and area exploration of block matching algorithms mapped on programmable processors. ICIP (3) 2001: 728-731
13	EE	I. Thoidis, Dimitrios Soudris, J. M. Fernandez, Adonios Thanailakis: The circuit design of multiple-valued logic voltage-mode adders. ISCAS (4) 2001: 162-165
12	EE	D. J. Soudris, M. M. Dasigenis, S. K. Vasilopoulou, Adonios Thanailakis: A CAD tool for architecture level exploration and automatic generation of RNS converters. ISCAS (4) 2001: 730-733
2000
11	EE	Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis: Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. PATMOS 2000: 243-254
1999
10	EE	M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, G. A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis: The VLSI implementation of a baseband receiver for DECT-based portable applications. ISCAS (1) 1999: 198-201
1998
9	EE	I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis: Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. Great Lakes Symposium on VLSI 1998: 83-88
1997
8	EE	Panagiotis Tzionas, Adonios Thanailakis, Phillipos Tsalides: An efficient algorithm for the largest empty figure problem based on a 2D cellular automaton architecture. Image Vision Comput. 15(1): 35-45 (1997)
7	EE	Ioannis Karafyllidis, A. Ioannidis, Adonios Thanailakis, Phillipos Tsalides: Geometrical Shape Recognition Using a Cellular Automaton Architecture and its VLSI Implementation. Real-Time Imaging 3(4): 243-254 (1997)
1996
6	EE	Ioannis Karafyllidis, Ioannis Andreadis, Panagiotis Tzionas, Phillipos Tsalides, Adonios Thanailakis: A cellular automaton for the determination of the mean velocity of moving objects and its VLSI implementation. Pattern Recognition 29(4): 689-699 (1996)
1995
5	EE	Panagiotis Tzionas, Phillipos Tsalides, Adonios Thanailakis: A Parallel Skeletonization Algorithm Based on Two-Dimensional Cellular Automata and its VLSI Implementation. Real-Time Imaging 1(2): 105-117 (1995)
1992
4		E. D. Adamides, Phillipos Tsalides, Adonios Thanailakis: Hierarchical Cellular Automata structures. Parallel Computing 18(5): 517-524 (1992)
1989
3		E. D. Adamides, Phillipos Tsalides, Adonios Thanailakis: Synchronization of D. Parkinsonasynchronous concurrent processes using cellular automata. Parallel Computing 11(2): 163-169 (1989)
1986
2		Werner Pries, Adonios Thanailakis, Howard C. Card: Group Properties of Cellular Automata and VLSI Applications. IEEE Trans. Computers 35(12): 1013-1024 (1986)
1		Howard C. Card, Adonios Thanailakis, Werner Pries, Robert D. McLeod: Analysis of Bounded Linear Cellular Automata Based on a Method of Image Charges. J. Comput. Syst. Sci. 33(3): 473-480 (1986)

Coauthor Index

1	E. D. Adamides	[3] [4]
2	Ioannis Andreadis	[6]
3	Antonios Argyriou	[11] [14] [18] [44]
4	David Atienza	[27] [35] [46] [52] [53]
5	Christos Baloukas	[35] [46]
6	Alexandros Bartzas	[52] [53]
7	Spyros Blionas	[17] [22] [24] [29]
8	Erik Brockmeyer	[28] [36] [42] [45] [55]
9	Howard C. Card	[1] [2]
10	Francky Catthoor	[27] [28] [35] [36] [42] [45] [46] [52] [53] [55]
11	M. M. Dasigenis	[12]
12	Minas Dasygenis	[11] [14] [18] [28] [36] [37] [39] [42] [44] [45] [55]
13	Chrissavgi Dre	[10]
14	Bart Durinck	[28] [42] [45] [55]
15	J. M. Fernandez	[13]
16	Constantinos E. Goutis (Costas E. Goutis)	[10] [11] [14] [15]
17	A. Ioannidis	[7]
18	Vasilios Kalenteridis	[30] [33] [43]
19	G. A. Kalivas	[10]
20	Ioannis Karafyllidis	[6] [7] [9] [16] [19] [26] [34]
21	C. Katis	[10]
22	Marios Kesoulis	[20] [24]
23	C. Koukourlis	[20] [24]
24	George Koutroumpezis	[17] [30] [31] [33] [38] [41] [43] [54]
25	Nikolas Kroupis	[14] [18] [37] [39] [44]
26	Stylianos Mamagkakis (Stelios Mamagkakis)	[27] [35] [46] [52] [53] [56]
27	K. Markou	[37]
28	Kostas Masselos (Konstantinos Masselos)	[17] [22] [29]
29	Robert D. McLeod	[1]
30	Jose Manuel Mendias (José M. Mendías)	[27] [35]
31	E. G. Metaxakis	[10]
32	Alexandros Mpartzas	[27]
33	Spiridon Nikolaidis	[21] [30] [33] [43]
34	Ilias Pappas	[30] [33] [43]
35	Vasilis F. Pavlidis	[23]
36	M. Perakis	[10]
37	Konstantinos Potamianos	[22] [29]
38	Georgios Pouiklis	[27] [52] [53]
39	Haroula Pournara	[30] [33] [43]
40	Werner Pries	[1] [2]
41	V. Raptis	[34]
42	K. Sgouropoulos	[23]
43	D. Siomos	[32]
44	Kostas Siozios (K. Siozios)	[21] [22] [25] [30] [31] [33] [38] [40] [41] [43] [47] [48] [49] [50] [51] [56]
45	Georgios Ch. Sirakoulis	[16] [19] [34]
46	Stilianos Siskos	[21] [30] [33] [43]
47	Dimitrios Soudris (D. J. Soudris)	[9] [10] [11] [12] [13] [14] [15] [17] [18] [20] [21] [22] [23] [24] [25] [27] [28] [29] [30] [31] [32] [33] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56]
48	Thanos Stouraitis	[9] [10]
49	Konstantinos Tatas (K. Tatas)	[11] [14] [17] [18] [21] [22] [23] [25] [29] [30] [31] [32] [33] [38] [41] [43] [44] [50] [51] [54]
50	Evaggelia Theochari	[29]
51	George Theodoridis	[15]
52	S. Theoharis	[15]
53	I. Thoidis	[9] [13]
54	Phillipos Tsalides	[3] [4] [5] [6] [7] [8] [34]
55	Ioannis Tsimperidis	[26]
56	A. E. Tzimas	[10]
57	Panagiotis Tzionas	[5] [6] [8]
58	S. K. Vasilopoulou	[12]
59	Nikolaos Vassiliadis	[21] [33] [43]
60	Nikolaos D. Zervas	[11] [14] [44]

Colors in the list of coauthors