 | 2001 |
|---|
| 11 |       | Subramania Sharma,
Matthew Thazhuthaveetil:
TWLinuX : Operating System Support for Optimistic Parallel Discrete Event Simulation.
HiPC 2001: 262-271 |
| 1995 |
|---|
| 10 |  | Mazin S. Yousif,
Matthew Thazhuthaveetil,
Chita R. Das:
Cache Coherence in Multiprocessors: A Survey.
Advances in Computers 40: 127-179 (1995) |
| 1993 |
|---|
| 9 | | Mazin S. Yousif,
Chita R. Das,
Matthew Thazhuthaveetil:
A Cache Coherence Protocol for MIN-Based Multprocessors With Limited Inclusion.
ICPP 1993: 254-257 |
| 1991 |
|---|
| 8 | | Mazin S. Algudady,
Chita R. Das,
Matthew Thazhuthaveetil:
A Cache-Based Checkpointing Scheme for MIN-Based Multiprocessors.
ICPP (1) 1991: 497-500 |
| 7 | | Lizy Kurian John,
Matthew Thazhuthaveetil:
Effect of Hot Spots on Multiprocessor Systems Using Circuit Switched Interconnection Networks.
ICPP (1) 1991: 554-557 |
| 1990 |
|---|
| 6 | | Robert L. Lesher,
Matthew Thazhuthaveetil:
Hotspot Contention in Non-Blocking Multistage Interconnection Networks.
ICPP (1) 1990: 401-404 |
| 5 | | Mazin S. Algudady,
Chita R. Das,
Matthew Thazhuthaveetil:
A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches.
SC 1990: 544-553 |
| 4 | | Chita R. Das,
Jeffrey T. Kreulen,
Matthew Thazhuthaveetil,
Laxmi N. Bhuyan:
Dependability Modeling for Multiprocessors.
IEEE Computer 23(10): 7-19 (1990) |
| 1987 |
|---|
| 3 | | Andrew R. Pleszkun,
Matthew Thazhuthaveetil:
The Architecture of Lisp Machines.
IEEE Computer 20(3): 35-44 (1987) |
| 2 | | Matthew Thazhuthaveetil,
Andrew R. Pleszkun:
On the Structural Locality of Reference in LISP List Access Streams.
Inf. Process. Lett. 26(2): 105-110 (1987) |
| 1986 |
|---|
| 1 | | Andrew R. Pleszkun,
Matthew Thazhuthaveetil:
An Architecture for Efficient Lisp List Access.
ISCA 1986: 191-198 |
