Donald E. Thomas

	2007
65		Brett H. Meyer, Donald E. Thomas: Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. CODES+ISSS 2007: 3-8
64		Alex Bobrek, JoAnn M. Paul, Donald E. Thomas: Event-based re-training of statistical contention models for heterogeneous multiprocessors. CODES+ISSS 2007: 69-74
63		Alex Bobrek, JoAnn M. Paul, Donald E. Thomas: Shared Resource Access Attributes for High-Level Contention Models. DAC 2007: 720-725
62		Brett H. Meyer, Donald E. Thomas: Rethinking Automated Synthesis of MPSoC Architectures. IPDPS 2007: 1-6
	2006
61		JoAnn M. Paul, Donald E. Thomas, Alex Bobrek: Scenario-oriented design for single-chip heterogeneous multiprocessors. IEEE Trans. VLSI Syst. 14(8): 868-880 (2006)
	2005
60		JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy: High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ACM Trans. Design Autom. Electr. Syst. 10(3): 431-461 (2005)
59		Philip Koopman, Howie Choset, Rajeev Gandhi, Bruce H. Krogh, Diana Marculescu, Priya Narasimhan, JoAnn M. Paul, Ragunathan Rajkumar, Daniel P. Siewiorek, Asim Smailagic, Peter Steenkiste, Donald E. Thomas, Chenxi Wang: Undergraduate embedded system education at Carnegie Mellon. ACM Trans. Embedded Comput. Syst. 4(3): 500-528 (2005)
	2004
58		JoAnn M. Paul, Donald E. Thomas, Alex Bobrek: Benchmark-based design strategies for single chip heterogeneous multiprocessors. CODES+ISSS 2004: 54-59
57		Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim: High level cache simulation for heterogeneous multiprocessors. DAC 2004: 287-292
56		Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. DATE 2004: 1144-1149
	2003
55		JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas: Schedulers as model-based design elements in programmable heterogeneous multiprocessors. DAC 2003: 408-411
54		Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas: Layered, Multi-Threaded, High-Level Performance Design. DATE 2003: 10954-10959
	2002
53		JoAnn M. Paul, Christopher M. Eatedali, Donald E. Thomas: The design context of concurrent computation systems. CODES 2002: 19-24
52		JoAnn M. Paul, Donald E. Thomas: A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. DATE 2002: 522-528
51		JoAnn M. Paul, Arne J. Suppé, Henele I. Adams, Donald E. Thomas: Multi-Level Modeling of Software on Hardware in Concurrent Computation. IPDPS 2002
50		Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul: System-Level Modeling of a Network Switch SoC. ISSS 2002: 62-67
	2001
49		Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas: Modeling and evaluation of hardware/software designs. CODES 2001: 11-16
48		JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas: Modeling and simulation of steady state and transient behaviors for emergent SoCs. ISSS 2001: 262-267
47		Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas: Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. IEEE Trans. VLSI Syst. 9(6): 805-812 (2001)
	2000
46		JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas: Frequency interleaving as a codesign scheduling paradigm. CODES 2000: 131-135
45		JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas: A codesign virtual machine for hierarchical, balanced hardware/software system modeling. DAC 2000: 390-395
44		William E. Dougherty, Donald E. Thomas: Unifying behavioral synthesis and physical design. DAC 2000: 756-761
43		Sari L. Coumeri, Donald E. Thomas: Memory modeling for system synthesis. IEEE Trans. VLSI Syst. 8(3): 327-334 (2000)
	1999
42		Donald E. Thomas, JoAnn M. Paul, Simon N. Peffers, Sandra J. Weber: Peer-based multithreaded executable co-specification. CODES 1999: 105-109
41		Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass: Vertical Benchmarks for CAD. DAC 1999: 408-413
40		Sari L. Coumeri, Donald E. Thomas: An Environment for Exploring Low Power Memory Configurations in System Level Design. ICCD 1999: 348-353
39		William E. Dougherty, Donald E. Thomas: Modeling and automating selection of guarding techniques for datapath elements. ISLPED 1999: 182-187
38		William E. Dougherty, David J. Pursley, Donald E. Thomas: Subsetting Behavioral Intellectual Property for Low Power ASIP Design. VLSI Signal Processing 21(3): 209-218 (1999)
	1998
37		Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas: Managing Pipeline-Reconfigurable FPGAs. FPGA 1998: 55-64
36		Sari L. Coumeri, Donald E. Thomas: Memory modeling for system synthesis. ISLPED 1998: 179-184
35		Herman Schmit, Donald E. Thomas: Address generation for memories containing multiple arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 377-385 (1998)
	1997
34		Herman Schmit, Donald E. Thomas: Synthesis of application-specific memory designs. IEEE Trans. VLSI Syst. 5(1): 101-111 (1997)
	1996
33		Jay K. Adams, Donald E. Thomas: The Design of Mixed Hardware/Software Systems. DAC 1996: 515-520
	1995
32		Prashant Sawkar, Donald E. Thomas: Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs. DAC 1995: 201-205
31		Herman Schmit, Donald E. Thomas: Hidden Markov modeling and fuzzy controllers in FPGAs. FCCM 1995: 214-221
30		Herman Schmit, Donald E. Thomas: Address generation for memories containing multiple arrays. ICCAD 1995: 510-514
29		Jay K. Adams, John Alan Miller, Donald E. Thomas: Execution-time profiling for multiple-process behavioral synthesis. ICCD 1995: 144-149
28		Jay K. Adams, Donald E. Thomas: Multiple-process behavioral synthesis for mixed hardware-software systems. ISSS 1995: 10-15
27		Herman Schmit, Donald E. Thomas: Array mapping in behavioral synthesis. ISSS 1995: 90-95
	1994
26		Lawrence F. Arnstein, Donald E. Thomas: The Attributed-Behavior Abstraction and Synthesis Tools. DAC 1994: 557-561
25		R. S. Ramchandani, Donald E. Thomas: Behavioral-Test Generation using Mixed-Integer Non-linear Programming. ITC 1994: 958-967
24		D. L. Springer, Donald E. Thomas: Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 843-856 (1994)
	1993
23		Prashant Sawkar, Donald E. Thomas: Performance Directed Technology Mapping for Look-Up Table Based FPGAs. DAC 1993: 208-212
22		Richard J. Cloutier, Donald E. Thomas: Synthesis of Pipelined Instruction Set Processors. DAC 1993: 583-588
21		Lawrence F. Arnstein, Donald E. Thomas: A general consistency technique for increasing the controllability of high level synthesis tools. ICCAD 1993: 741-744
20		Donald E. Thomas, Jay K. Adams, Herman Schmit: A Model and Methodology for Hardware-Software Codesign. IEEE Design & Test of Computers 10(3): 6-15 (1993)
	1992
19		Prashant Sawkar, Donald E. Thomas: Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays. DAC 1992: 368-373
18		Jay K. Adams, Donald E. Thomas: Addressing the Tradeoff Between Standard and Custom ICs in System Level Design. ICCD 1992: 194-197
	1991
17		Elizabeth D. Lagnese, Donald E. Thomas: Architectural partitioning for system level synthesis of integrated circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 847-860 (1991)
	1990
16		Richard J. Cloutier, Donald E. Thomas: The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm. DAC 1990: 71-76
15		D. L. Springer, Donald E. Thomas: Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis. ICCAD 1990: 254-257
	1989
14		Elizabeth D. Lagnese, Donald E. Thomas: Architectural Partitioning for System Level Design. DAC 1989: 62-67
13		Robert A. Walker, Donald E. Thomas: Behavioral transformation for algorithmic level IC design. IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1115-1128 (1989)
	1988
12		Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn: The System Architect's Workbench. DAC 1988: 337-343
11		Robert L. Blackburn, Donald E. Thomas, Patti M. Koenig: CORAL II: Linking Behavior and Structure in an IC Design System. DAC 1988: 529-535
	1987
10		Donald E. Thomas, Robert L. Blackburn, Jayanth V. Rajan: Linking the Behavioral and Structural Domains of Representation for Digital System Design. IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 103-110 (1987)
	1985
9		Donald E. Thomas: Observations on comparing digital systems synthesis techniques. ACM Conference on Computer Science 1985: 17-22
8		Thaddeus J. Kowalski, Donald E. Thomas: The VLSI design automation assistant: what's in a knowledge base. DAC 1985: 252-258
7		Jayanth V. Rajan, Donald E. Thomas: Synthesis by delayed binding of decisions. DAC 1985: 367-373
6		Robert L. Blackburn, Donald E. Thomas: Linking the behavioral and structural dominis of representation in a synthesis system. DAC 1985: 374-380
5		Robert A. Walker, Donald E. Thomas: A model of design representation and synthesis. DAC 1985: 453-459
	1983
4		Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, Robert A. Walker: Automatic Data Path Synthesis. IEEE Computer 16(12): 59-70 (1983)
3		Donald E. Thomas, G. W. Leive: Automating Technology Relative Logic Synthesis and Module Selection. IEEE Trans. on CAD of Integrated Circuits and Systems 2(2): 94-105 (1983)
2		Donald E. Thomas, John A. Nestor: Defining and Implementing a Multilevel Design Representation with Simulation Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 135-145 (1983)
	1981
1		Donald E. Thomas, Daniel P. Siewiorek: Measuring Designer Performance to Verify Design Automation Systems. IEEE Trans. Computers 30(1): 48-61 (1981)

Coauthor Index

1	Henele I. Adams	[51]
2	Jay K. Adams	[18] [20] [28] [29] [33]
3	Christopher P. Andrews	[50]
4	Lawrence F. Arnstein	[21] [26]
5	Robert L. Blackburn	[6] [10] [11] [12]
6	Alex Bobrek	[55] [56] [58] [61] [63] [64]
7	Srihari Cadambi	[37]
8	Andrew S. Cassidy	[50] [54] [60]
9	Howie Choset	[59]
10	Richard J. Cloutier	[16] [22]
11	Sari L. Coumeri	[36] [40] [43]
12	Elizabeth M. Dirkes	[12]
13	William E. Dougherty	[38] [39] [44]
14	Christopher M. Eatedali	[53]
15	Rajeev Gandhi	[59]
16	Seth Copen Goldstein	[37]
17	Charles Y. Hitchcock III	[4]
18	Christopher Inacio	[41]
19	Faraydon Karim	[57]
20	Ben Klass	[41]
21	Patti M. Koenig	[11]
22	Philip Koopman (Phil Koopman, Philip J. Koopman Jr.)	[59]
23	Thaddeus J. Kowalski	[4] [8]
24	Bruce H. Krogh	[59]
25	Elizabeth D. Lagnese	[14] [17]
26	G. W. Leive	[3]
27	Diana Marculescu	[59]
28	Alain Mellan	[57]
29	Brett H. Meyer	[62] [65]
30	John Alan Miller	[29]
31	David Nagle	[41]
32	Priya Narasimhan	[59]
33	Jeffrey E. Nelson	[55] [56]
34	John A. Nestor	[2] [12]
35	JoAnn M. Paul	[42] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [63] [64]
36	Simon N. Peffers	[42] [45] [46]
37	Joshua J. Pieper	[55] [56] [57]
38	David J. Pursley	[38]
39	Jayanth V. Rajan	[4] [7] [10] [12]
40	Ragunathan Rajkumar	[59]
41	R. S. Ramchandani	[25]
42	Andrew Ryan	[41]
43	Prashant Sawkar	[19] [23] [32]
44	Herman Schmit	[20] [27] [30] [31] [34] [35] [37] [41]
45	Daniel P. Siewiorek	[1] [59]
46	Asim Smailagic	[59]
47	D. L. Springer	[15] [24]
48	Peter Steenkiste	[59]
49	Arne J. Suppé	[48] [51]
50	Neal K. Tibrewala	[49]
51	Yingfai Tong	[41]
52	Robert A. Walker	[4] [5] [12] [13]
53	Chenxi Wang	[59]
54	Sandra J. Weber	[42] [47]
55	Jeffrey Weener	[37]

Colors in the list of coauthors