Donald E. Thomas

	2010
81		Adam S. Hartman, Donald E. Thomas, Brett H. Meyer: A case for lifetime-aware task mapping in embedded chip multiprocessors. CODES+ISSS 2010: 145-154
80		Brett H. Meyer, Adam S. Hartman, Donald E. Thomas: Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs. DATE 2010: 1596-1601
79		Brett H. Meyer, Adam S. Hartman, Donald E. Thomas: Slack allocation for yield improvement in NoC-based MPSoCs. ISQED 2010: 738-746
78		Alex Bobrek, JoAnn M. Paul, Donald E. Thomas: Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors. IEEE Trans. Computers 59(10): 1402-1418 (2010)
	2009
77		Brett H. Meyer, Donald E. Thomas: Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC. Design Autom. for Emb. Sys. 13(1-2): 73-88 (2009)
	2007
76		Brett H. Meyer, Donald E. Thomas: Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. CODES+ISSS 2007: 3-8
75		Alex Bobrek, JoAnn M. Paul, Donald E. Thomas: Event-based re-training of statistical contention models for heterogeneous multiprocessors. CODES+ISSS 2007: 69-74
74		Alex Bobrek, JoAnn M. Paul, Donald E. Thomas: Shared Resource Access Attributes for High-Level Contention Models. DAC 2007: 720-725
73		Brett H. Meyer, Donald E. Thomas: Rethinking Automated Synthesis of MPSoC Architectures. IPDPS 2007: 1-6
	2006
72		JoAnn M. Paul, Donald E. Thomas, Alex Bobrek: Scenario-oriented design for single-chip heterogeneous multiprocessors. IEEE Trans. VLSI Syst. 14(8): 868-880 (2006)
	2005
71		JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy: High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ACM Trans. Design Autom. Electr. Syst. 10(3): 431-461 (2005)
70		Philip Koopman, Howie Choset, Rajeev Gandhi, Bruce H. Krogh, Diana Marculescu, Priya Narasimhan, JoAnn M. Paul, Ragunathan Rajkumar, Daniel P. Siewiorek, Asim Smailagic, Peter Steenkiste, Donald E. Thomas, Chenxi Wang: Undergraduate embedded system education at Carnegie Mellon. ACM Trans. Embedded Comput. Syst. 4(3): 500-528 (2005)
	2004
69		JoAnn M. Paul, Donald E. Thomas, Alex Bobrek: Benchmark-based design strategies for single chip heterogeneous multiprocessors. CODES+ISSS 2004: 54-59
68		Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim: High level cache simulation for heterogeneous multiprocessors. DAC 2004: 287-292
67		Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. DATE 2004: 1144-1149
	2003
66		JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas: Schedulers as model-based design elements in programmable heterogeneous multiprocessors. DAC 2003: 408-411
65		Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas: Layered, Multi-Threaded, High-Level Performance Design. DATE 2003: 10954-10959
	2002
64		JoAnn M. Paul, Christopher M. Eatedali, Donald E. Thomas: The design context of concurrent computation systems. CODES 2002: 19-24
63		JoAnn M. Paul, Donald E. Thomas: A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. DATE 2002: 522-528
62		JoAnn M. Paul, Arne J. Suppé, Henele I. Adams, Donald E. Thomas: Multi-Level Modeling of Software on Hardware in Concurrent Computation. IPDPS 2002
61		Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul: System-Level Modeling of a Network Switch SoC. ISSS 2002: 62-67
	2001
60		Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas: Modeling and evaluation of hardware/software designs. CODES 2001: 11-16
59		JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas: Modeling and simulation of steady state and transient behaviors for emergent SoCs. ISSS 2001: 262-267
58		Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas: Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. IEEE Trans. VLSI Syst. 9(6): 805-812 (2001)
	2000
57		JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas: Frequency interleaving as a codesign scheduling paradigm. CODES 2000: 131-135
56		JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas: A codesign virtual machine for hierarchical, balanced hardware/software system modeling. DAC 2000: 390-395
55		William E. Dougherty, Donald E. Thomas: Unifying behavioral synthesis and physical design. DAC 2000: 756-761
54		Sari L. Coumeri, Donald E. Thomas: Memory modeling for system synthesis. IEEE Trans. VLSI Syst. 8(3): 327-334 (2000)
	1999
53		Donald E. Thomas, JoAnn M. Paul, Simon N. Peffers, Sandra J. Weber: Peer-based multithreaded executable co-specification. CODES 1999: 105-109
52		Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass: Vertical Benchmarks for CAD. DAC 1999: 408-413
51		Sari L. Coumeri, Donald E. Thomas: An Environment for Exploring Low Power Memory Configurations in System Level Design. ICCD 1999: 348-353
50		William E. Dougherty, Donald E. Thomas: Modeling and automating selection of guarding techniques for datapath elements. ISLPED 1999: 182-187
49		William E. Dougherty, David J. Pursley, Donald E. Thomas: Subsetting Behavioral Intellectual Property for Low Power ASIP Design. VLSI Signal Processing 21(3): 209-218 (1999)
	1998
48		Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas: Managing Pipeline-Reconfigurable FPGAs. FPGA 1998: 55-64
47		Sari L. Coumeri, Donald E. Thomas: Memory modeling for system synthesis. ISLPED 1998: 179-184
46		Herman Schmit, Donald E. Thomas: Address generation for memories containing multiple arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 377-385 (1998)
	1997
45		Herman Schmit, Donald E. Thomas: Synthesis of application-specific memory designs. IEEE Trans. VLSI Syst. 5(1): 101-111 (1997)
	1996
44		Donald E. Thomas, Philip Moorby: The Verilog hardware description language (3. ed.). Kluwer 1996: I-XVI, 1-310
43		Jay K. Adams, Donald E. Thomas: The Design of Mixed Hardware/Software Systems. DAC 1996: 515-520
	1995
42		Donald E. Thomas, Philip Moorby: The Verilog hardware description language (2. ed.). Kluwer 1995: I-XVI, 1-275
41		Prashant Sawkar, Donald E. Thomas: Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs. DAC 1995: 201-205
40		Herman Schmit, Donald E. Thomas: Hidden Markov modeling and fuzzy controllers in FPGAs. FCCM 1995: 214-221
39		Herman Schmit, Donald E. Thomas: Address generation for memories containing multiple arrays. ICCAD 1995: 510-514
38		Jay K. Adams, John Alan Miller, Donald E. Thomas: Execution-time profiling for multiple-process behavioral synthesis. ICCD 1995: 144-149
37		Jay K. Adams, Donald E. Thomas: Multiple-process behavioral synthesis for mixed hardware-software systems. ISSS 1995: 10-15
36		Herman Schmit, Donald E. Thomas: Array mapping in behavioral synthesis. ISSS 1995: 90-95
	1994
35		Lawrence F. Arnstein, Donald E. Thomas: The Attributed-Behavior Abstraction and Synthesis Tools. DAC 1994: 557-561
34		R. S. Ramchandani, Donald E. Thomas: Behavioral-Test Generation using Mixed-Integer Non-linear Programming. ITC 1994: 958-967
33		D. L. Springer, Donald E. Thomas: Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 843-856 (1994)
	1993
32		Prashant Sawkar, Donald E. Thomas: Performance Directed Technology Mapping for Look-Up Table Based FPGAs. DAC 1993: 208-212
31		Richard J. Cloutier, Donald E. Thomas: Synthesis of Pipelined Instruction Set Processors. DAC 1993: 583-588
30		Lawrence F. Arnstein, Donald E. Thomas: A general consistency technique for increasing the controllability of high level synthesis tools. ICCAD 1993: 741-744
29		Donald E. Thomas, Jay K. Adams, Herman Schmit: A Model and Methodology for Hardware-Software Codesign. IEEE Design & Test of Computers 10(3): 6-15 (1993)
	1992
28		Prashant Sawkar, Donald E. Thomas: Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays. DAC 1992: 368-373
27		Jay K. Adams, Donald E. Thomas: Addressing the Tradeoff Between Standard and Custom ICs in System Level Design. ICCD 1992: 194-197
	1991
26		Elizabeth D. Lagnese, Donald E. Thomas: Architectural partitioning for system level synthesis of integrated circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 847-860 (1991)
	1990
25		Richard J. Cloutier, Donald E. Thomas: The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm. DAC 1990: 71-76
24		D. L. Springer, Donald E. Thomas: Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis. ICCAD 1990: 254-257
	1989
23		Donald E. Thomas: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989. ACM Press 1989
22		Elizabeth D. Lagnese, Donald E. Thomas: Architectural Partitioning for System Level Design. DAC 1989: 62-67
21		Robert A. Walker, Donald E. Thomas: Behavioral transformation for algorithmic level IC design. IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1115-1128 (1989)
	1988
20		Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn: The System Architect's Workbench. DAC 1988: 337-343
19		Robert L. Blackburn, Donald E. Thomas, Patti M. Koenig: CORAL II: Linking Behavior and Structure in an IC Design System. DAC 1988: 529-535
	1987
18		Donald E. Thomas, Robert L. Blackburn, Jayanth V. Rajan: Linking the Behavioral and Structural Domains of Representation for Digital System Design. IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 103-110 (1987)
	1985
17		Donald E. Thomas: Observations on comparing digital systems synthesis techniques. ACM Conference on Computer Science 1985: 17-22
16		Thaddeus J. Kowalski, Donald E. Thomas: The VLSI design automation assistant: what's in a knowledge base. DAC 1985: 252-258
15		Jayanth V. Rajan, Donald E. Thomas: Synthesis by delayed binding of decisions. DAC 1985: 367-373
14		Robert L. Blackburn, Donald E. Thomas: Linking the behavioral and structural dominis of representation in a synthesis system. DAC 1985: 374-380
13		Robert A. Walker, Donald E. Thomas: A model of design representation and synthesis. DAC 1985: 453-459
	1983
12		Thaddeus J. Kowalski, Donald E. Thomas: The VLSI Design Automation Assistant: Prototype system. DAC 1983: 479-483
11		Charles Y. Hitchcock III, Donald E. Thomas: A method of automatic data path synthesis. DAC 1983: 484-489
10		Robert A. Walker, Donald E. Thomas: Behavioral level transformation in the CMU-DA system. DAC 1983: 788-789
9		Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, Robert A. Walker: Automatic Data Path Synthesis. IEEE Computer 16(12): 59-70 (1983)
8		Donald E. Thomas, G. W. Leive: Automating Technology Relative Logic Synthesis and Module Selection. IEEE Trans. on CAD of Integrated Circuits and Systems 2(2): 94-105 (1983)
7		Donald E. Thomas, John A. Nestor: Defining and Implementing a Multilevel Design Representation with Simulation Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 135-145 (1983)
	1982
6		John A. Nestor, Donald E. Thomas: Defining and implementing a multilevel design representation with simulation applications. DAC 1982: 740-746
	1981
5		G. W. Leive, Donald E. Thomas: A technology relative Logic Synthesis and Module Selection system. DAC 1981: 479-485
4		Donald E. Thomas, Daniel P. Siewiorek: Measuring Designer Performance to Verify Design Automation Systems. IEEE Trans. Computers 30(1): 48-61 (1981)
	1979
3		Alice C. Parker, Donald E. Thomas, Daniel P. Siewiorek, Mario Barbacci, Louis J. Hafer, G. W. Leive, Jinchoon Kim: The CMU design automation system: An example of automated data path design. DAC 1979: 73-80
	1978
2		Edward A. Snow, Daniel P. Siewiorek, Donald E. Thomas: A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs. DAC 1978: 220-226
	1977
1		Donald E. Thomas, Daniel P. Siewiorek: Measuring designer performance to verify design automation systems. DAC 1977: 411-418

Coauthor Index

1	Henele I. Adams	[62]
2	Jay K. Adams	[27] [29] [37] [38] [43]
3	Christopher P. Andrews	[61]
4	Lawrence F. Arnstein	[30] [35]
5	Mario Barbacci	[3]
6	Robert L. Blackburn	[14] [18] [19] [20]
7	Alex Bobrek	[66] [67] [69] [72] [74] [75] [78]
8	Srihari Cadambi	[48]
9	Andrew S. Cassidy	[61] [65] [71]
10	Howie Choset	[70]
11	Richard J. Cloutier	[25] [31]
12	Sari L. Coumeri	[47] [51] [54]
13	Elizabeth M. Dirkes	[20]
14	William E. Dougherty	[49] [50] [55]
15	Christopher M. Eatedali	[64]
16	Rajeev Gandhi	[70]
17	Seth Copen Goldstein	[48]
18	Louis J. Hafer	[3]
19	Adam S. Hartman	[79] [80] [81]
20	Charles Y. Hitchcock III	[9] [11]
21	Christopher Inacio	[52]
22	Faraydon Karim	[68]
23	Jinchoon Kim	[3]
24	Ben Klass	[52]
25	Patti M. Koenig	[19]
26	Philip Koopman (Phil Koopman, Philip J. Koopman Jr.)	[70]
27	Thaddeus J. Kowalski	[9] [12] [16]
28	Bruce H. Krogh	[70]
29	Elizabeth D. Lagnese	[22] [26]
30	G. W. Leive	[3] [5] [8]
31	Diana Marculescu	[70]
32	Alain Mellan	[68]
33	Brett H. Meyer	[73] [76] [77] [79] [80] [81]
34	John Alan Miller	[38]
35	Philip Moorby	[42] [44]
36	David Nagle	[52]
37	Priya Narasimhan	[70]
38	Jeffrey E. Nelson	[66] [67]
39	John A. Nestor	[6] [7] [20]
40	Alice C. Parker	[3]
41	JoAnn M. Paul	[53] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71] [72] [74] [75] [78]
42	Simon N. Peffers	[53] [56] [57]
43	Joshua J. Pieper	[66] [67] [68]
44	David J. Pursley	[49]
45	Jayanth V. Rajan	[9] [15] [18] [20]
46	Ragunathan Rajkumar (Raj Rajkumar)	[70]
47	R. S. Ramchandani	[34]
48	Andrew Ryan	[52]
49	Prashant Sawkar	[28] [32] [41]
50	Herman Schmit	[29] [36] [39] [40] [45] [46] [48] [52]
51	Daniel P. Siewiorek	[1] [2] [3] [4] [70]
52	Asim Smailagic	[70]
53	Edward A. Snow	[2]
54	D. L. Springer	[24] [33]
55	Peter Steenkiste	[70]
56	Arne J. Suppé	[59] [62]
57	Neal K. Tibrewala	[60]
58	Yingfai Tong	[52]
59	Robert A. Walker	[9] [10] [13] [20] [21]
60	Chenxi Wang	[70]
61	Sandra J. Weber	[53] [58]
62	Jeffrey Weener	[48]

Colors in the list of coauthors

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