Arthit Thongtak

	2008
3		Thanasin Bunnam, Arthit Thongtak: An Approach for the Delay Simulation of D-Inverter in C-Ternary Logic Circuits. CDES 2008: 224-228
2		Sufian Sudeng, Arthit Thongtak: Template Based: A Novel STG Based Logic Synthesis for Asynchronous Control Circuits. World Congress on Engineering (Selected Papers) 2008: 59-74
	1998
1		Arthit Thongtak, Takashi Nanya: Stuck-at-fault testing for quasi-delay-insensitive logic circuits. Systems and Computers in Japan 29(2): 19-27 (1998)

Coauthor Index

1	Thanasin Bunnam	[3]
2	Takashi Nanya	[1]
3	Sufian Sudeng	[2]

Colors in the list of coauthors