 | 1992 |
|---|
| 6 |       | Gerhard W. Dueck,
Robert C. Earle,
Parthasarathy P. Tirumalai,
Jon T. Butler:
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing.
ISMVL 1992: 66-74 |
| 5 |  | B. Ramakrishna Rau,
Michael S. Schlansker,
Parthasarathy P. Tirumalai:
Code generation schema for modulo scheduled loops.
MICRO 1992: 158-169 |
| 4 | | B. Ramakrishna Rau,
M. Lee,
Parthasarathy P. Tirumalai,
Michael S. Schlansker:
Register Allocation for Software Pipelined Loops.
PLDI 1992: 283-299 |
| 1991 |
|---|
| 3 | | Parthasarathy P. Tirumalai,
Varadarajan G. Vadakkencherry:
Parallel Algorithms for Minimizing Multiple-Valued Programmable Logic Arrays.
ISMVL 1991: 287-295 |
| 2 | | Parthasarathy P. Tirumalai,
Jon T. Butler:
Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.
IEEE Trans. Computers 40(2): 167-177 (1991) |
| 1990 |
|---|
| 1 | | Parthasarathy P. Tirumalai,
M. Lee,
Michael S. Schlansker:
Parallelization of loops with exits on pipelined architectures.
SC 1990: 200-212 |
