 | 1993 |
|---|
| 5 |       | Eiichi Teraoka,
Toru Kengaku,
Ikuo Yasui,
Kazuyuki Ishikawa,
Takahiro Matsuo,
Hideyuki Wakada,
Narumi Sakashita,
Yukihiko Shimazu,
Takeshi Tokuda:
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC.
ITC 1993: 791-796 |
| 1991 |
|---|
| 4 | | Toshiyuki Tamura,
Shinji Komori,
Fumiyasu Asai,
Hirono Tsubota,
Hisakazu Sato,
Hidehiro Takata,
Yoshihiro Seguchi,
Takeshi Tokuda,
Hiroaki Terada:
A Data-Driven Architecture for Distributed Parallel Processing.
ICCD 1991: 218-224 |
| 1988 |
|---|
| 3 |  | Takeshi Tokuda,
Jiro Korematsu,
Yukihiko Shimazu,
Narumi Sakashita,
Tohru Kengaku,
Toshiki Fugiyama,
Takio Ohno,
Osamu Tomisawa:
A macrocell approach for VLSI processor design.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(12): 1272-1277 (1988) |
| 1984 |
|---|
| 2 | | Takeshi Tokuda,
Jiro Korematsu,
Osamu Tomisawa,
S. Asai,
I. Ohkura,
T. Enomoto:
A Hierarchical Standard Cell Approach for Custom VLSI Design.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 172-177 (1984) |
| 1983 |
|---|
| 1 | | Takeshi Tokuda,
Kaoru Okazaki,
K. Sakashita,
I. Ohkura,
T. Enomoto:
Delay-Time Modeling for ED MOS Logic LSI.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 129-134 (1983) |
