Hiroyuki Tomiyama

	2009
37		Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada: Analyzing and optimizing energy efficiency of algorithms on DVS systems a first step towards algorithmic energy minimization. ASP-DAC 2009: 727-732
36		Gang Zeng, Tetsuo Yokoyama, Hiroyuki Tomiyama, Hiroaki Takada: Practical Energy-Aware Scheduling for Real-Time Multiprocessor Systems. RTCSA 2009: 383-392
35		Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada: Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model. IEICE Transactions 92-D(7): 1412-1420 (2009)
	2008
34		Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue: Improved Policies for Drowsy Caches in Embedded Processors. DELTA 2008: 362-367
33		Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Tohru Ishihara: A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. EUC (1) 2008: 206-213
32		Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: CHStone: A benchmark program suite for practical C-based high-level synthesis. ISCAS 2008: 1192-1195
31		Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori, Hiroyuki Kanbara, Hiroyuki Tomiyama: High-Level Synthesis of Software Function Calls. IEICE Transactions 91-A(12): 3556-3558 (2008)
30		Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada: An Effective GA-Based Scheduling Algorithm for FlexRay Systems. IEICE Transactions 91-D(8): 2115-2123 (2008)
	2007
29		Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. ACM Great Lakes Symposium on VLSI 2007: 365-370
28		Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada: RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. ASP-DAC 2007: 336-341
27		Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada: A Software Framework for Energy and Performance Tradeoff in Fixed-Priority Hard Real-Time Embedded Systems. EUC 2007: 13-24
26		Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. ICESS 2007: 261-270
25		Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada: A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems. ICESS 2007: 283-294
24		Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada: Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services. IESS 2007: 241-254
23		Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada: Scheduling Algorithms for I/O Blockings with a Multi-frame Task Model. RTCSA 2007: 386-393
22		Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis. IEICE Transactions 90-A(12): 2853-2862 (2007)
21		Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: Function Call Optimization for Efficient Behavioral Synthesis. IEICE Transactions 90-A(9): 2032-2036 (2007)
	2006
20		Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: Function Call Optimization in Behavioral Synthesis. DSD 2006: 522-529
	2005
19		Shan Ding, Naohiko Murakami, Hiroyuki Tomiyama, Hiroaki Takada: A GA-based scheduling method for FlexRay systems. EMSOFT 2005: 110-113
18		Hiroshi Miyamoto, Shinichi Iiyama, Hiroyuki Tomiyama, Hiroaki Takada, Hiroshi Nakashima: An Efficient Search Algorithm of Worst-Case Cache Flush Timings. RTCSA 2005: 45-52
17		Hiroyuki Tomiyama, Shin-ichiro Chikada, Shinya Honda, Hiroaki Takada: An RTOS-Based Design and Validation Methodology for Embedded Systems. IEICE Transactions 88-D(9): 2205-2208 (2005)
	2004
16		Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada: RTOS-centric hardware/software cosimulator for embedded system design. CODES+ISSS 2004: 158-163
	2003
15		Hiroyuki Tomiyama, Hiroaki Takada, Nikil D. Dutt: Data Organization Exploration for Low-Energy Address Buses. ESTImedia 2003: 128-133
	2002
14		Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama: Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. DATE 2002: 36-43
13		Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao: Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. ISSS 2002: 201-206
12		Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. VLSI Design 2002: 458-
	2001
11		Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama, Ashok Halambi: New directions in compiler technology for embedded systems (embedded tutorial). ASP-DAC 2001: 409-414
10		Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt: Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. VLSI Design 2001: 97-102
	2000
9		Hiroyuki Tomiyama, Nikil D. Dutt: Program path analysis to bound cache-related preemption delay in preemptive real-time systems. CODES 2000: 67-71
	1998
8		Hiroyuki Tomiyama, Hiroto Yasuura: Module Selection Using Manufacturing Information. ASP-DAC 1998: 275-281
7		Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura: Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE 1998: 855-860
6		Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura: Instruction Encoding Techniques for Area Minimization of Instruction ROM. ISSS 1998: 125-130
5		Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura: Statistical Performance-Driven Module Binding in High-Level Synthesis. ISSS 1998: 66-71
4		Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar: Embedded System Design Using Soft-Core Processor and Valen-C. J. Inf. Sci. Eng. 14(3): 587-603 (1998)
	1997
3		Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura: Memory-CPU Size Optimization for Embedded System Designs. DAC 1997: 246-251
2		Hiroyuki Tomiyama, Hiroto Yasuura: Code placement techniques for cache miss rate reduction. ACM Trans. Design Autom. Electr. Syst. 2(4): 410-429 (1997)
	1996
1		Hiroyuki Tomiyama, Hiroto Yasuura: Size-Constrained Code Placement for Cache Miss Rate Reduction. ISSS 1996: 96-104

Coauthor Index

1	Anupam Basu	[10]
2	Yun Cao	[13]
3	Shin-ichiro Chikada	[17]
4	Sidharth Choudhury	[10]
5	Anupam Datta	[10]
6	Shan Ding	[19] [23] [30] [35]
7	Nikil D. Dutt (Nikil Dutt)	[9] [10] [11] [12] [14] [15]
8	Eko Fajar	[4] [6]
9	Takashi Furukawa	[25]
10	Peter Grun	[12]
11	Ashok Halambi	[11] [12]
12	Yuko Hara	[20] [21] [22] [26] [29] [32]
13	Shinya Honda	[16] [17] [20] [21] [22] [25] [26] [28] [29] [32]
14	Shinichi Iiyama	[18]
15	Akihiko Inoue	[4] [5] [6] [7]
16	Koji Inoue	[34]
17	Tohru Ishihara	[7] [33]
18	Katsuya Ishii	[22] [26] [29] [32]
19	Yoshiyuki Ishimori	[31]
20	Nagisa Ishiura	[31]
21	Hiroyuki Kanbara	[31]
22	Hisao Koizumi	[3]
23	Prabhat Mishra	[12] [14]
24	Hiroshi Miyamoto	[18]
25	Naohiko Murakami	[19]
26	Hiroshi Nakashima	[18]
27	Alexandru Nicolau (Alex Nicolau)	[11] [12] [14]
28	Masanari Nishimura	[31]
29	Takanori Okuma	[6] [13]
30	Etsuko Okushi	[3]
31	Barry Shackleford	[3]
32	Hiroaki Takada	[15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [32] [33] [34] [35] [36] [37]
33	Takayuki Wakabayashi	[16]
34	Mitsuhiro Yasuda	[3]
35	Hiroto Yasuura	[1] [2] [3] [4] [5] [6] [7] [8] [13]
36	Tetsuo Yokoyama	[36] [37]
37	Gang Zeng	[24] [27] [33] [34] [36] [37]
38	Junpei Zushi	[34]