 | 2008 |
|---|
| 5 |       | Hiroaki Nishikawa,
Hiroshi Tomiyasu,
Hiroyuki Uchida:
VLSI Design of Networking-Oriented Chip Multi-Processor; CUE-v3.
PDPTA 2008: 655-661 |
| 2007 |
|---|
| 4 | | Hiroaki Nishikawa,
Hiroshi Tomiyasu,
Masanobu Okamoto,
Masayoshi Sugiyama,
Hiroyuki Uchida,
Osamu Mizuno,
Hiroshi Ishii,
Makoto Iwata:
CUE-v3: Data-Driven Chip Multi-Processor for Ad hoc and Ubiquitous Networking Environment.
PDPTA 2007: 623-629 |
| 2004 |
|---|
| 3 | | Shinya Ito,
Shouhei Nomoto,
Hiroshi Tomiyasu,
Hiroaki Nishikawa:
The Microarchitecture of the CUE-v2 Processor: Enabling the Simultaneous Processing of Dataflow and Control-Flow Threads.
PDPTA 2004: 525-531 |
| 1999 |
|---|
| 2 | | Zsolt Németh,
Hiroshi Tomiyasu,
Péter Kacsuk,
Makoto Amamiya:
Multithreaded LOGFLOW on KUMP/D.
ISHPC 1999: 320-327 |
| 1997 |
|---|
| 1 |  | Hiroshi Tomiyasu,
Shigeru Kusakabe,
Tetsuo Kawano,
Makoto Amamiya:
Co-processor System Design for Fine-Grain Message Handling in KUMP/D.
Euro-Par 1997: 779-788 |
