 | 2007 |
| 12 |  | Suleyman Tosun,
Nazanin Mansouri,
Ercument Arvas,
Mahmut T. Kandemir,
Yuan Xie:
Reliability-Centric High-Level Synthesis
CoRR abs/0710.4684: (2007) |
| 2006 |
| 11 |  | Ozcan Ozturk,
Mahmut T. Kandemir,
Suleyman Tosun:
An ILP based approach to address code generation for digital signal processors.
ACM Great Lakes Symposium on VLSI 2006: 37-42 |
| 10 |  | Sirzat Kahramanli,
Suleyman Tosun:
A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization.
CDES 2006: 10-16 |
| 9 |  | Suleyman Tosun,
Mahmut T. Kandemir,
Hakduran Koc:
Using Task Recomputation During Application Mapping in Parallel Embedded Architectures.
CDES 2006: 29-35 |
| 8 |  | Ozcan Ozturk,
Mahmut T. Kandemir,
Mary Jane Irwin,
Suleyman Tosun:
Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors.
ICPADS (1) 2006: 383-390 |
| 7 |  | Suleyman Tosun,
Nazanin Mansouri,
Mahmut T. Kandemir,
Ozcan Ozturk:
An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors.
ISCIS 2006: 267-276 |
| 6 |  | Hakduran Koc,
Suleyman Tosun,
Ozcan Ozturk,
Mahmut T. Kandemir:
Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems.
ISVLSI 2006: 448-449 |
| 2005 |
| 5 |  | Suleyman Tosun,
Nazanin Mansouri,
Ercument Arvas,
Mahmut T. Kandemir,
Yuan Xie:
Reliability-Centric High-Level Synthesis.
DATE 2005: 1258-1263 |
| 4 |  | Guilin Chen,
Mahmut T. Kandemir,
Suleyman Tosun,
Ugur Sezer:
Reliability-Conscious Process Scheduling under Performance Constraints in FPGA-Based Embedded Systems.
IPDPS 2005 |
| 3 |  | Suleyman Tosun,
Ozcan Ozturk,
Nazanin Mansouri,
Ercument Arvas,
Mahmut T. Kandemir,
Yuan Xie,
Wei-Lun Hung:
An ILP Formulation for Reliability-Oriented High-Level Synthesis.
ISQED 2005: 364-369 |
| 2 |  | Suleyman Tosun,
Nazanin Mansouri,
Ercument Arvas,
Mahmut T. Kandemir,
Yuan Xie,
Wei-Lun Hung:
Reliability-Centric Hardware/Software Co-Design.
ISQED 2005: 375-380 |
| 2003 |
| 1 |  | Suleyman Tosun,
Hakduran Koc,
Nazanin Mansouri:
Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs.
VLSI 2003: 382- |