| 2005 | ||
|---|---|---|
| 5 | Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David Brooks: An Ultra Low Power System Architecture for Sensor Network Applications. ISCA 2005: 208-219 | |
| 2004 | ||
| 4 | Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, R. Anderson, J. R. Uribe: Overview of a compiler for synthesizing MATLAB programs onto FPGAs. IEEE Trans. VLSI Syst. 12(3): 312-324 (2004) | |
| 2003 | ||
| 3 | Prithviraj Banerjee, Vikram Saxena, J. R. Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, R. Anderson: Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. FPGA 2003: 237 | |
| 2002 | ||
| 2 | Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi: A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs. IWDC 2002: 246-256 | |
| 2001 | ||
| 1 | Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal: Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. VLSI Design 2001: 227- | |
| 1 | R. Anderson | [3] [4] |
| 2 | Debabrata Bagchi | [2] [3] [4] |
| 3 | Prithviraj Banerjee (Prith Banerjee) | [2] [3] [4] |
| 4 | Amit M. Bhosle | [1] |
| 5 | David Brooks | [5] |
| 6 | Malay Haldar | [2] [3] [4] |
| 7 | Mark Hempstead | [5] |
| 8 | Victor Kim | [2] [3] [4] |
| 9 | Patrick Mauro | [5] |
| 10 | Anshuman Nayak | [2] [3] [4] |
| 11 | Ajit Pal | [1] |
| 12 | Satrajit Pal | [2] [3] [4] |
| 13 | Steven Parkes | [4] |
| 14 | Debasis Samanta | [1] |
| 15 | Vikram Saxena | [3] [4] |
| 16 | J. R. Uribe | [3] [4] |
| 17 | Gu-Yeon Wei | [5] |
| 18 | David Zaretsky | [4] |
Colors in the list of coauthors
Last update Fri May 25 01:42:58 2012 CET by the DBLP Team —
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