 | 2009 |
|---|
| 12 |       | Chen Kang Lo,
Ren-Song Tsay:
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model.
ASP-DAC 2009: 558-563 |
| 11 | | Yi-Len Lo,
Mao Lin Li,
Ren-Song Tsay:
Cycle count accurate memory modeling in system level design.
CODES+ISSS 2009: 287-294 |
| 10 | | Meng-Huan Wu,
Cheng-Yang Fu,
Peng-Chih Wang,
Ren-Song Tsay:
An effective synchronization approach for fast and accurate multi-core instruction-set simulation.
EMSOFT 2009: 197-204 |
| 2008 |
|---|
| 9 | | Ching-Te Chiu,
Tsun-Hsien Wang,
Wei-Ming Ke,
Chen-Yu Chuang,
Jhih-Rong Chen,
Rong Yang,
Ren-Song Tsay:
Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video.
ICIP 2008: 1400-1403 |
| 8 | | Ching-Te Chiu,
Tsun-Hsien Wang,
Wei-Ming Ke,
Chen-Yu Chuang,
Jhih-Siao Huang,
Wei-Su Wong,
Ren-Song Tsay:
A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology.
SiPS 2008: 25-30 |
| 1993 |
|---|
| 7 | | Ren-Song Tsay:
An exact zero-skew clock routing algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(2): 242-249 (1993) |
| 1992 |
|---|
| 6 | | Minshine Shih,
Ernest S. Kuh,
Ren-Song Tsay:
Performance-Driven System Partitioning on Multi-Chip Modules.
DAC 1992: 53-56 |
| 1991 |
|---|
| 5 | | Ren-Song Tsay,
Jürgen Koehl:
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement.
DAC 1991: 620-625 |
| 4 |  | Ren-Song Tsay:
Exact Zero Skew.
ICCAD 1991: 336-339 |
| 3 | | Gopalakrishnan Vijayan,
Ren-Song Tsay:
A new method for floor planning using topological constraint reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1494-1501 (1991) |
| 1990 |
|---|
| 2 | | Gopalakrishnan Vijayan,
Ren-Song Tsay:
Floorplanning by Topological Constraint Reduction.
ICCAD 1990: 106-109 |
| 1988 |
|---|
| 1 | | Ren-Song Tsay,
Ernest S. Kuh,
Chi-Ping Hsu:
Proud: A Fast Sea-of-Gates Placement Algorithm.
DAC 1988: 318-323 |
